Circuit board, light-emitting substrate, backlight module, and display apparatus

Patent metadata

Field	Value
Publication number	US-12457685-B2
Application number	US-202218552754-A
Country	US
Kind code	B2
Filing date	Oct 31, 2022
Priority date	Oct 31, 2022
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

A circuit board includes a substrate, a first conductive layer, a first insulating layer and a second conductive layer. The first conductive layer includes a plurality of first conductive portions. The second conductive layer includes a plurality of second conductive portions. A second conductive portion passes through a first via hole in the first insulating layer to be in electrical contact with a first conductive portion. The first conductive layer and the second conductive layer each include at least one main conductive layer, which is capable of creating a first intermetallic compound with solder. At least one of the first conductive layer and the second conductive layer further includes a stop layer capable of creating a second intermetallic compound with the solder. A rate of a reaction between the stop layer and the solder is lower than a rate of a reaction between the main conductive layer and the solder.

First claim

What is claimed is:

1 . A circuit board, comprising:
a substrate; a first conductive layer disposed on a side of the substrate; the first conductive layer including a plurality of signal lines and a plurality of first conductive portions; a first insulating layer disposed on a side of the first conductive layer away from the substrate; the first insulating layer being provided with first via holes extending through the first insulating layer; and a second conductive layer disposed on a side of the first insulating layer away from the substrate; the second conductive layer including a plurality of second conductive portions; a second conductive portion passing through a first via hole to be in electrical contact with a first conductive portion; the second conductive portion including a plurality of pads, and a pad being a portion of the second conductive portion exposed by the first via hole in the first insulating layer; wherein the first conductive layer and the second conductive layer each include at least one main conductive layer, and the main conductive layer is configured to be capable of creating a first intermetallic compound with solder; at least one of the first conductive layer and the second conductive layer further includes a stop layer, and the stop layer is disposed between two adjacent main conductive layers and is configured to be capable of creating a second intermetallic compound with the solder; and a rate of a reaction between the stop layer and the solder is lower than a rate of a reaction between the main conductive layer and the solder.

2 . The circuit board according to claim 1 , wherein a material of the stop layer includes any of nickel, a copper alloy with a copper atomic percentage greater than 40% and a nickel alloy with a nickel atomic percentage greater than 40%.

3 . The circuit board according to claim 1 , wherein a thickness of the stop layer is in a range of 100 Å to 5000 Å, inclusive.

4 . The circuit board according to claim 1 , further comprising an anti-oxidation layer, wherein the anti-oxidation layer is disposed on a side of the second conductive layer away from the substrate, and the anti-oxidation layer is configured to be capable of creating a third intermetallic compound with the solder.

5 . The circuit board according to claim 4 , wherein the second conductive layer further includes traces, and the anti-oxidation layer encompasses both the traces and the second conductive portions in the second conductive layer.

6 . The circuit board according to claim 4 , wherein a material of the anti-oxidation layer includes nickel or a nickel alloy with a nickel atomic percentage greater than 40%.

7 . The circuit board according to claim 4 , wherein a thickness of the anti-oxidation layer is in a range of 100 Å to 40000 Å, inclusive.

8 . The circuit board according to claim 1 , wherein the first conductive layer further includes an adhesive layer, and the adhesive layer is disposed between a main conductive layer of the first conductive layer and the substrate, and the adhesive layer is not capable of reacting with the solder.

9 . The circuit board according to claim 8 , wherein a material of the adhesive layer includes any of titanium, molybdenum, a molybdenum-niobium alloy, a molybdenum-titanium alloy, a molybdenum-tungsten alloy, a molybdenum-tantalum alloy, and a molybdenum-niobium-titanium alloy.

10 . The circuit board according to claim 8 , wherein a thickness of the adhesive layer is in a range of 100 Å to 2000 Å, inclusive.

11 . The circuit board according to claim 1 , wherein an area of an orthogonal projection of the first conductive portion on the substrate is greater than an area of an orthogonal projection of the pad on the substrate, and the orthogonal projection of the pad on the substrate is located with the orthogonal projection of the first conductive portion on the substrate.

12 . The circuit board according to claim 1 , wherein the first conductive layer includes a single main conductive layer and a single stop layer, the second conductive layer includes another single main conductive layer and another single stop layer, and two stop layers are located between the single main conductive layer of the first conductive layer and the another single main conductive layer of the second conductive layer; or
the first conductive layer includes a single main conductive layer, the second conductive layer includes another single main conductive layer and a single stop layer, and the single stop layer is located between the single main conductive layer of the first conductive layer and the another single main conductive layer of the second conductive layer; or the first conductive layer includes a single main conductive layer and a single stop layer, the second conductive layer includes another single main conductive layer, and the single stop layer is located between the single main conductive layer of the first conductive layer and the another single main conductive layer of the second conductive layer.

13 . The circuit board according to claim 1 , wherein the plurality of second conductive portions are divided into a plurality of device conductive portion groups and a plurality of chip conductive portion groups;
the circuit board comprises a plurality of driving units arranged in an array, and each driving unit includes multiple device conductive portion groups in the plurality of device conductive portion groups; the circuit board further comprises: a plurality of connection lines, wherein the multiple device conductive portion groups in a same driving unit are electrically connected by connection lines, and the plurality of connection lines are located in the first conductive layer and/or the second conductive layer.

14 . The circuit board according to claim 1 , wherein the plurality of second conductive portions are divided into a plurality of device conductive portion groups and a plurality of chip conductive portion groups;
the signal lines include a first signal line and a second signal line; the first signal line is electrically connected to a device conductive portion group, and the second signal line is electrically connected to a chip conductive portion group; and the first insulating layer is further provided with second via holes extending through the first insulating layer; the circuit board further comprises: a plurality of device transfer lines located in the second conductive layer, wherein an end of a device transfer line is in electrical contact with the first signal line through a second via hole, and another end thereof is in electrical contact with the device conductive portion group; and a plurality of chip transfer lines located in the second conductive layer, wherein an end of a chip transfer line is in electrical contact with the second signal line through another second via hole, and another end thereof is in electrical contact with the chip conductive portion group.

15 . The circuit board according to claim 1 , further comprising:
a first passivation layer disposed between the first conductive layer and the first insulating layer and at least exposing part of the first conductive portion; and a second passivation layer disposed between the first insulating layer and the second conductive layer and at least exposing part of the first conductive portion; wherein multiple pads in the plurality of pads configured to be electrically connected to a same electronic component are exposed by a same first via hole, so that the first insulating layer does not exist in a region between the multiple pads.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Yao Nianqi
• Zhao Kun
• Ning ce
• Li Zhengliang
• Cao Zhanfeng
• Wang Ke
• Zhang Jiaxiang
• Qi Qi
• Hu hehe
• Li Feifei
• Huang Jie
• He Jiayu

Classifications

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H05K2201/2054

  Light-reflecting surface, e.g. conductors, substrates, coatings, dielectrics · CPC title

• H05K2201/10106

  Light emitting diode [LED] · CPC title

• H05K3/282

  for inhibiting the corrosion of the circuit, e.g. for preserving the solderability · CPC title

• H05K1/116

  Lands, clearance holes or other lay-out details concerning the surrounding of a via · CPC title