NIC priority queue steering and processor unit frequency tuning based on packet flow analytics

US12457178B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12457178-B2
Application numberUS-202117359303-A
CountryUS
Kind codeB2
Filing dateJun 25, 2021
Priority dateJun 25, 2021
Publication dateOct 28, 2025
Grant dateOct 28, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In one embodiment, a system comprises a network interface controller comprising circuitry to determine per-flow analytics information for a plurality of packet flows that are received at the network interface controller and to facilitate differential rate processing of a plurality of packet queues for the plurality of packet flows based on the per-flow analytics information.

First claim

Opening claim text (preview).

What is claimed is: 1 . A system comprising: a network interface controller comprising circuitry to: determine per-flow analytics information for a plurality of packet flows that are received at the network interface controller and provided from the network interface controller to a plurality of processor units; and facilitate differential rate processing by the plurality of processor units of a plurality of packet queues for the plurality of packet flows based on the per-flow analytics information, wherein a first packet flow of the plurality of packet flows is assigned to a first packet queue of the plurality of packet queues based upon sizes of packets of the first packet flow. 2 . The system of claim 1 , wherein the per-flow analytics information comprises per-flow size metrics for the plurality of packet flows. 3 . The system of claim 2 , wherein the per-flow size metrics comprise an average packet size of a packet flow. 4 . The system of claim 1 , wherein the differential rate processing comprises polling of the plurality of packet queues by a plurality of processor units set to operate at different frequencies. 5 . The system of claim 1 , wherein the differential rate processing comprises changing a frequency of a processor unit polling a packet queue of the plurality of packet queues. 6 . The system of claim 1 , wherein facilitating differential rate processing comprises steering the plurality of packet flows to the plurality of packet queues based on the per-flow analytics information. 7 . The system of claim 1 , wherein facilitating differential rate processing comprises providing at least a portion of the per-flow analytics information to a host computing system for use in a determination of whether to adjust an operating frequency of a processor unit polling a packet queue of the plurality of packet queues. 8 . The system of claim 1 , wherein facilitating differential rate processing comprises assigning a packet flow to a default packet queue based on per-flow analytics information for the packet flow and subsequently providing a portion of the per-flow analytics information to a host computing system responsive to a burst of packets of the packet flow for use in determination of whether to raise an operating frequency of a processor unit polling the default packet queue. 9 . The system of claim 1 , wherein the circuitry of the network interface controller is further to, based on sizes of a plurality of packets of the first packet flow, send information to cause a processing unit that is processing packets of the first packet queue to increase its frequency. 10 . The system of claim 1 , wherein the circuitry of the network interface controller is further to assign a packet flow to a high priority packet queue based on a determination that the packet flow includes packets of a relatively small size, wherein the high priority packet queue is processed at a higher frequency than at least one other packet queue to which the network interface controller assigns packet flows. 11 . A method comprising: determining, by a network interface controller, per-flow analytics information for a plurality of packet flows received by a network interface controller; and facilitating differential rate processing of a plurality of packet queues for the plurality of packet flows based on the per-flow analytics information, wherein a first packet flow of the plurality of packet flows is assigned to a first packet queue of the plurality of packet queues based upon sizes of packets of the first packet flow. 12 . The method of claim 11 , wherein the per-flow analytics information comprises per-flow size metrics for the plurality of packet flows. 13 . The method of claim 12 , wherein the per-flow size metrics comprise an average packet size of a packet flow. 14 . The method of claim 11 , wherein the differential rate processing comprises polling of a plurality of packet queues by a plurality of processor units set to operate at different frequencies. 15 . The method of claim 11 , wherein the differential rate processing comprises changing a frequency of a processor unit polling a packet queue of the plurality of packet queues. 16 . A system comprising: a plurality of processor units, wherein at least one of the plurality of processor units is to poll a plurality of packet queues of a network interface controller; and circuitry to implement differential rate processing of the plurality of packet queues by the plurality of processor units based on per-flow analytics information generated by the network interface controller, wherein a frequency at which a processor unit processes packets of a packet flow is based on sizes of packets of the packet flow. 17 . The system of claim 16 , wherein implementing differential rate processing of the plurality of packet queues comprises assigning processor units operating at different frequencies to poll the plurality of packet queues. 18 . The system of claim 16 , wherein implementing differential rate processing of the plurality of packet queues comprises dynamically varying a frequency of a processor unit of the plurality of processor units based on at least a portion of the per-flow analytics information generated by the network interface controller. 19 . The system of claim 18 , wherein the circuitry is to set a timer in association with a change in the frequency of the processor unit and to cause the processor unit to revert back to a default frequency upon expiration of the timer. 20 . The system of claim 18 , wherein dynamically varying the frequency of the processor unit of the plurality of processor units is further based on platform data of a host computing system comprising the processor units. 21 . The system of claim 20 , wherein the platform data comprises a power budget for at least a portion of the host computing system. 22 . The system of claim 16 , wherein the per-flow analytics information generated by the network interface controller comprises an analytics score for a packet flow. 23 . One or more non-transitory computer-readable media with code stored thereon, wherein the code is executable to cause a machine to: implement differential rate processing, by a plurality of processor units, of a plurality of packet queues of a network interface controller based on per-flow analytics information generated by the network interface controller, wherein a packet flow is assigned to be processed by a processor unit of the plurality of processor units based on sizes of packets of the packet flow. 24 . The media of claim 23 , wherein implementing differential rate processing of the plurality of packet queues comprises assigning processor units operating at different frequencies to poll the plurality of packet queues. 25 . The media of claim 23 , wherein the code is to cause the machine to implement differential rate processing of the plurality of packet queues by dynamically varying a frequency of a processor unit of the plurality of processor units based on at least a portion of the per-flow analytics information generated by the network interface controller. 26 . The media of claim 25 , wherein the code is to cause the machine to set a timer in association with a change in the frequency of the processor unit and to cause the processor unit to revert back to a default frequency upon expiration of the timer.

Assignees

Inventors

Classifications

  • based on packet size, e.g. shortest packet first · CPC title

  • QOS or priority aware · CPC title

  • Rate modification at the source after receiving feedback · CPC title

  • relying on flow classification, e.g. using integrated services [IntServ] · CPC title

  • Collecting or measuring resource availability data · CPC title

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Frequently asked questions

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What does patent US12457178B2 cover?
In one embodiment, a system comprises a network interface controller comprising circuitry to determine per-flow analytics information for a plurality of packet flows that are received at the network interface controller and to facilitate differential rate processing of a plurality of packet queues for the plurality of packet flows based on the per-flow analytics information.
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification H04L47/627. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 28 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 9 related publications on this page (citations in our corpus or others sharing the same primary CPC).