Packet header field extraction

US12457172B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12457172-B2
Application numberUS-202418734862-A
CountryUS
Kind codeB2
Filing dateJun 5, 2024
Priority dateAug 26, 2015
Publication dateOct 28, 2025
Grant dateOct 28, 2025

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline.

First claim

Opening claim text (preview).

What is claimed is: 1. At least one non-transitory machine readable medium storing program instructions for being executed by at least one machine, the program instructions being for use in association with generation of configuration data for use in programming, at least in part, at least one packet processing pipeline associated with network switch hardware, the at least one packet processing pipeline being configurable to comprise at least one parser stage, at least one match-action stage, and at least one other stage, the at least one packet processing pipeline being configurable to process ingress packet data to generate egress packet data, the program instructions, when executed by the at least one machine, resulting in the at least one machine being configured for performing operations comprising: generating the configuration data based upon compilation of programming language code, the programming language code being user-generated, at least in part, the programming language code being configurable to describe, at least in part: header field parsing, by the at least one parser stage, of the ingress packet data; and header field matching and/or header field modifying, at least in part, by the at least one match-action stage, of the ingress packet data; wherein: when the network switch hardware is in the operation, the network switch hardware is to associate respective subsets of header field data of the ingress packet data with each other in respective sets of memory locations; the respective sets of memory locations are for use by the at least one match-action stage and the at least one other stage, respectively; and the at least one other stage is configurable to generate, at least in part, the egress packet data based upon (1) at least one unmodified header field of the at least one ingress packet as parsed by the at least one parser stage and (2) at least one other header field generated, at least in part, by the at least one match-action stage as a result of the header field modifying. 2. The at least one non-transitory machine readable medium of claim 1 , wherein: the ingress packet data comprises packet header data; and the programming language code is configurable to describe, at least in part, at least one parse graph that indicates, at least in part, manner in which the at least one parser stage is (1) to parse, at least in part, packet header data and (2) to identify from the packet header data the respective subsets of header field data. 3. The at least one non-transitory machine readable medium of claim 1 , wherein: the network switch hardware is configurable for use with both ternary content addressable memory (TCAM) and other memory; the TCAM and the other memory are to store match-action table data to be used by the at least one match-action stage in the header field matching and/or header field modifying, at least in part; and the match-action table data is configurable, based upon the configuration data, to indicate tunneling encapsulation-related operations. 4. A method implemented, at least in part, using program instructions for being executed by at least one machine, the program instructions being for use in association with generation of configuration data for use in programming, at least in part, at least one packet processing pipeline associated with network switch hardware, the at least one packet processing pipeline being configurable to comprise at least one parser stage, at least one match-action stage, and at least one other stage, the at least one packet processing pipeline being configurable to process ingress packet data to generate egress packet data, the method comprising: executing, by the at least one machine, the program instructions, the program instructions, when executed by the at least one machine, permitting generation of the configuration data based upon compilation of programming language code, the programming language code being user-generated, at least in part, the programming language code being configurable to describe, at least in part: header field parsing, by the at least one parser stage, of the ingress packet data; and header field matching and/or header field modifying, at least in part, by the at least one match-action stage, of the ingress packet data; wherein: when the network switch hardware is in the operation, the network switch hardware is to associate respective subsets of header field data of the ingress packet data with each other in respective sets of memory locations; the respective sets of memory locations are for use by the at least one match-action stage and the at least one other stage, respectively; and the at least one other stage is configurable to generate, at least in part, the egress packet data based upon (1) at least one unmodified header field of the at least one ingress packet as parsed by the at least one parser stage and (2) at least one other header field generated, at least in part, by the at least one match-action stage as a result of the header field modifying. 5. The method of claim 4 , wherein: the ingress packet data comprises packet header data; and the programming language code is configurable to describe, at least in part, at least one parse graph that indicates, at least in part, manner in which the at least one parser stage is (1) to parse, at least in part, packet header data and (2) to identify from the packet header data the respective subsets of header field data. 6. The method of claim 4 , wherein: the network switch hardware is configurable for use with both ternary content addressable memory (TCAM) and other memory; the TCAM and the other memory are to store match-action table data to be used by the at least one match-action stage in the header field matching and/or header field modifying, at least in part; and the match-action table data is configurable, based upon the configuration data, to indicate tunneling encapsulation-related operations. 7. At least one packet processing pipeline for use in association with network switch hardware, the at least one packet processing pipeline comprising: at least one parser stage; at least one match-action stage; and at least one other stage; wherein: the at least one packet processing pipeline is programmable, at least in part, via configuration data; the at least one packet processing pipeline is to process the ingress packet data to generate egress packet data; the configuration data is to be generated based upon compilation of programming language code; the programming language code is user-generated, at least in part; the programming language code is configurable to describe, at least in part: header field parsing, by the at least one parser stage, of the ingress packet data; and header field matching and/or header field modifying, at least in part, by the at least one match-action stage, of the ingress packet data; when the network switch hardware is in the operation, the network switch hardware is to associate respective subsets of header field data of the ingress packet data with each other in respective sets of memory locations; the respective sets of memory locations are for use by the at least one match-action stage and the at least one other stage, respectively; and the at least one other stage is configurable to generate, at least in part, the egress packet data based upon (1) at least one unmodified header field of the at least one ingress packet as parsed by the at least one parser stage and (2) at least one other header field generated, at least in part, by the at least one match-action stage as a result of the header field modifying. 8. The at least one packet processing pipeline of claim 7 , wherein: the ingress packet data comprises pac

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What does patent US12457172B2 cover?
Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first …
Who is the assignee on this patent?
Barefoot Networks Inc
What technology area does this patent fall under?
Primary CPC classification H04L45/64. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 28 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).