Wireless circuitry with delay measurement and tuning

Patent metadata

Field	Value
Publication number	US-12456993-B2
Application number	US-202217941905-A
Country	US
Kind code	B2
Filing date	Sep 9, 2022
Priority date	Sep 9, 2022
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

Wireless circuitry can include a processor that generates a baseband signal, an upconversion circuit that upconverts the baseband signals to a radio-frequency signal, and an amplifier that amplifies the radio-frequency signal. A tunable delay circuit can be used to selectively delay generation of the radio-frequency signal or to delay generation of another signal intended for the radio-frequency amplifier. The tunable delay circuit can be controlled using a closed-loop delay adaptation scheme. A feedback receiver that is coupled to an output of the amplifier can be used to generate a demodulated signal. A delay error measurement circuit can be used to receive the demodulated signal, to detect a peak by monitoring when an envelope of the demodulated signal crosses a threshold level, to compute an amount of asymmetry in the detected peak, and to output a signal that is used to control the tunable delay circuit.

First claim

What is claimed is:

1 . Wireless circuitry comprising:
a radio-frequency amplifier having a first input configured to receive a radio-frequency signal, a second input, and an output; a tunable delay circuit configured to receive a baseband signal and configured to selectively delay the baseband signal when generating the radio-frequency signal for the first input of the radio-frequency amplifier or to selectively delay the baseband signal when generating a signal for the second input of the radio-frequency amplifier; a feedback receiver coupled to the output of the radio-frequency amplifier and configured to generate a corresponding baseband signal; and a delay error measurement circuit configured to output an error signal that is used to control the tunable delay circuit based on only the baseband signal generated by the feedback receiver.

2 . The wireless circuitry of claim 1 , wherein the second input of the radio-frequency amplifier comprises a power supply terminal, further comprising:
envelope tracking circuitry configured to output a variable power supply voltage to the power supply terminal of the radio-frequency amplifier.

3 . Wireless circuitry comprising:
a radio-frequency amplifier having a first input configured to receive a radio-frequency signal, a second input, and an output; a control signal generator configured to output a signal for the second input of the radio-frequency amplifier, the signal being used to tune an adjustable load component in the radio-frequency amplifier; a tunable delay circuit configured to receive a baseband signal and configured to selectively delay the baseband signal when generating the radio-frequency signal for the first input of the radio-frequency amplifier or to selectively delay the baseband signal when generating the signal for the second input of the radio-frequency amplifier; a feedback receiver coupled to the output of the radio-frequency amplifier and configured to generate a corresponding baseband signal; and a delay error measurement circuit configured to receive the corresponding baseband signal generated by the feedback receiver and to output an error signal that is used to control the tunable delay circuit.

4 . The wireless circuitry of claim 1 , wherein the delay error measurement circuit is further configured to detect one or more peaks in an envelope of the baseband signal and to output the error signal by computing an amount of asymmetry in the one or more detected peaks.

5 . The wireless circuitry of claim 4 , wherein the delay error measurement circuit is further configured to detect the one or more peaks by detecting when the envelope of the baseband signal rises above a threshold level.

6 . The wireless circuitry of claim 5 , wherein the delay error measurement circuit is further configured to output the error signal by averaging measurements from a plurality of detected peaks.

7 . The wireless circuitry of claim 4 , wherein the delay error measurement circuit is further configured to compute rise and fall times in the one or more detect peaks using interpolation.

8 . The wireless circuitry of claim 1 , further comprising:
a delay controller configured to receive the error signal and to output a delay control signal for adjusting the tunable delay circuit.

9 . The wireless circuitry of claim 1 , wherein the feedback receiver comprises:
a downconversion circuit coupled to the output of the radio-frequency amplifier; and an analog-to-digital converter configured to receive a signal from the downconversion circuit and to output the baseband signal.

10 . The wireless circuitry of claim 1 , wherein the delay error measurement circuit comprises:
a threshold detector configured to detect when an envelope of the baseband signal exceeds a threshold level; and a peak detector configured to detect a peak point in the envelope of the baseband signal.

11 . The wireless circuitry of claim 10 , wherein the delay error measurement circuit further comprises:
a rising edge measurement circuit configured to output a first value proportional to a rise time of a rising edge in the envelope of the baseband signal, the rise time extending from when the envelope exceeds the threshold level until the peak point; and a falling edge measurement circuit configured to output a second value proportional to a fall time of a falling edge in the envelope of the baseband signal, the fall time extending form when the envelope reaches the peak point until falling below the threshold level.

12 . The wireless circuitry of claim 11 , wherein the rising edge measurement circuit comprises a first counter circuit, and wherein the falling edge measurement circuit comprises a second counter circuit.

13 . The wireless circuitry of claim 11 , wherein the delay error measurement circuit further comprises a subtractor configured to compute a difference between the first and second values.

14 . The wireless circuitry of claim 13 , wherein the delay error measurement circuit further comprises a normalization block configured to scale the difference by a duration of the one or more detected peaks.

15 . The wireless circuitry of claim 13 , wherein the delay error measurement circuit further comprises a low pass filter configured to average the difference.

16 . The wireless circuitry of claim 11 , wherein:
the rising edge measurement circuit is configured to output the first value by performing a first interpolation operation; and the falling edge measurement circuit is configured to output the second value by performing a second interpolation operation.

17 . A method of operating wireless circuitry, comprising:
using a radio-frequency amplifier to amplify a radio-frequency signal; using a feedback receiver to receive a portion of the amplified radio-frequency signal and to output a demodulated signal; detecting one or more peaks in an envelope of the demodulated signal; computing an amount of asymmetry in the one or more detected peaks; and selectively delaying an input signal to the radio-frequency amplifier based on the computed amount of asymmetry.

18 . The method of claim 17 , wherein selectively delaying an input signal to the radio-frequency amplifier based on the computed amount of asymmetry comprises:
in response to determining that the one or more detected peaks are skewed in a first direction, delaying the radio-frequency signal; and in response to determining that the one or more detected peaks are skewed in a second direction different than the first direction, delaying a power supply voltage or a load impedance control signal for the radio-frequency amplifier.

19 . The method of claim 17 , further comprising:
averaging timing measurements obtained from multiple detected peaks; and performing interpolation to detect when the one or more peaks in the envelope crosses a threshold value.

20 . Circuitry comprising:
a radio-frequency amplifier; a tunable delay circuit coupled to one or more inputs of the radio-frequency amplifier; a measurement receiver coupled to an output of the radio-frequency amplifier and configured to generate a demodulated signal; and a symmetry detection circuit coupled to the radio-frequency amplifier and configured to
receive the demodulated signal,
detect a peak in an envelope of the demodulated signal crossing a threshold level,
compute an amount of asymmetry in the detected peak, and
output a control signal to the tunable delay circuit.

Assignees

• Apple Inc

Inventors

• Henzler Stephan
• Preyss Nicholas
• Schrattenecker Jochen
• Langer Andreas
• Klinkan Alexander
• Hepp Christoph
• Angerer Christoph

Classifications

• H04L5/0048

  Allocation of pilot signals, i.e. of signals known to the receiver (allocation of control signalling H04L5/0053; use of control signalling H04L5/0091) · CPC title

• H04W56/005 Primary

  compensating for timing error by adjustment in the receiver · CPC title

• H04B2001/0408

  with power amplifiers · CPC title

• H04B1/0458 Primary

  Arrangements for matching and coupling between power amplifier and antenna or between amplifying stages (matching circuits in general H03H) · CPC title

• H04W24/08

  Testing, {supervising or monitoring} using real traffic · CPC title