Pick-up structure for memory device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12456639-B2
Application number	US-202217751130-A
Country	US
Kind code	B2
Filing date	May 23, 2022
Priority date	Jul 23, 2021
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

A pick-up structure for a memory device and method for manufacturing memory device are provided. The pick-up structure includes a substrate and a plurality of pick-up electrode strips. The substrate has a memory cell region and a peripheral pick-up region adjacent thereto. The pick-up electrode strips are parallel to a first direction and arranged on the substrate in a second direction. The second direction is different from the first direction. Each pick-up electrode strip includes a main part in the peripheral pick-up region and an extension part extending from the main part to the memory cell region. The main part is defined by fork-shaped patterns of a first mask layer. The extension part has a width less than that of the main part, and the extension part has a side wall surface aligned with a side wall surface of the main part.

First claim

What is claimed is:

1. A pick-up structure for a memory device, comprising:
a substrate, having a memory cell region and a peripheral pick-up area adjacent to the memory cell area; and
a plurality of pick-up electrode strips, parallel to a first direction, extending along a second direction that is different from the first direction, and arranged on the substrate, wherein each of the pick-up electrode strips comprises:
a main part, deposited in the peripheral pick-up area, wherein the main part is defined by a plurality of fork-shaped patterns in a first mask layer; and
an extension part, extending from the main part to the memory cell region, wherein the extension part has a width less than a width of the main part and the extension part has a side wall surface aligned with a side wall surface of the main part;
wherein the first mask layer, a sacrificial material layer, and a second mask layer are sequentially formed on the substrate;
wherein a first pattern and a second pattern are formed in the second mask layer;
wherein the first pattern corresponds to the memory cell region and comprises a plurality of first strip patterns and a plurality of second strip patterns parallel with one another, and the second pattern corresponds to the peripheral pick-up region and comprises a plurality of fork-shaped patterns connected to the plurality of second strip patterns.

2. The pick-up structure for the memory device as defined in claim 1 , wherein each of the fork-shaped patterns comprises a first strip pattern, a second strip pattern, and a connection pattern, the first strip pattern and the second strip pattern are parallel to the first direction and extend along the second direction, and the connection pattern is configured to connect the first strip pattern and the second strip pattern, wherein the first strip pattern and the second strip pattern are configured to define the main part.

3. The pick-up structure for the memory device as defined in claim 1 , wherein a multi-layer resist structure covers the first strip pattern and the second strip pattern and is configured to form the extension part connecting the main part through the connection pattern, wherein the first strip pattern and the second strip pattern form the main part.

4. The pick-up structure for the memory device as defined in claim 1 , wherein the pick-up electrode strips at least comprise a first pick-up electrode strip, a second pick-up electrode strip, a third pick-up electrode strip, and a fourth pick-up electrode strip arranged along the second direction, wherein the main part of the pick-up electrode strips has the same width.

5. The pick-up structure for the memory device as defined in claim 4 , wherein one of the fork-shaped patterns defines the first pick-up electrode strip and the second pick-up electrode strip and another of the fork-shaped patterns defines the third pick-up electrode strip and the fourth pick-up electrode strip.

6. The pick-up structure for the memory device as defined in claim 4 , wherein the first pick-up electrode strip and the second pick-up electrode strip are symmetrically arranged with each other and the third pick-up electrode strip and the fourth pick-up electrode strip are symmetrically arranged with each other.

7. The pick-up structure for the memory device as defined in claim 4 , wherein the extension part of the first pick-up electrode strip and the extension part of the second pick-up electrode strip are separated with a first length and the main part of the first pick-up electrode strip and the main part of the second pick-up electrode strip are separated with a second length, wherein the first length exceeds the second length.

8. The pick-up structure for the memory device as defined in claim 7 , wherein the extension part of the third pick-up electrode strip and the extension part of the fourth pick-up electrode strip are separated with a third length and the main part of the third pick-up electrode strip and the main part of the fourth pick-up electrode strip are separated with a fourth length, wherein the third length exceeds the fourth length and the second length.

9. The pick-up structure for the memory device as defined in claim 7 , wherein the extension part of the second pick-up electrode strip and the extension part of the third pick-up electrode strip are separated with a third length and the main part of the second pick-up electrode strip and the main part of the third pick-up electrode strip are separated with a fourth length, wherein the third length is equal to the fourth length and the second length.

10. The pick-up structure for the memory device as defined in claim 1 , wherein the pick-up electrode strips at least comprise a first pick-up electrode strip, a second pick-up electrode strip, a third electrode strip, and a fourth electrode strip arranged along the second direction, wherein, the main part of the first pick-up electrode strip and the main part of the second pick-up electrode strip have the same first length, the main part of the third pick-up electrode strip and the main part of the fourth pick-up electrode strip have the same second length, wherein the first length exceeds the second length.

11. The pick-up structure for the memory device as defined in claim 1 ,
wherein each of the fork-shaped patterns comprises a third strip pattern, a fourth strip pattern, and a connection pattern, the third strip pattern and the fourth strip pattern are parallel to a first direction, and the connection pattern is configured to connect the third strip pattern and the fourth strip pattern.

12. The pick-up structure for the memory device as defined in claim 11 , wherein the first pattern and the second pattern in the second mask layer are transferred to the sacrificial material layer so that the sacrificial material layer has the first strip patterns, the second strip patterns, and the fork-shaped patterns;
wherein the second mask layer having the first pattern and the second pattern is removed;
wherein a plurality of spacer layers on the first mask layer is formed so that there is a corresponding spacer layer on two opposite side walls of each of the first strip patterns and two opposite side walls of each of the second strip patterns in the sacrificial material layer.

13. The pick-up structure for the memory device as defined in claim 12 , wherein a first etching on the first mask layer is performed by using the sacrificial material layer and the spacer layers as an etching mask;
wherein after the first etching, the sacrificial material layer is removed to leave the spacer layers;
wherein a second etching on the first mask layer is performed by using the spacer layers as an etching mask so that the first mask layer has a third pattern.

14. The pick-up structure for the memory device as defined in claim 13 , wherein before the second etching, a multi-layer resist structure is formed on the substrate to cover the spacer layers and the first mask layer so that the spacer layers and the multi-layer resist structure are configured as the etching mask during the second etching.

15. The pick-up structure for the memory device as defined in claim 14 , wherein the multi-layer resist structure further covers the spacer layers of the first strip patterns, the third strip pattern, and the fourth pattern and the first mask layer so that the connection pattern is removed during the second etching.

Assignees

• Winbond Electronics Corp
• Windbond Electronics Corp

Inventors

• Lin Tsung-Wei
• Liao Chun-Yen
• Wu Kun-Che
• Yang Cheng-Ta
• Wu Chun-Sheng

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10P72/72 Primary

  using electrostatic chucks · CPC title

• H10P72/0446

  Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates · CPC title