Non-volatile memory device, storage device having the same and operating method of non-volatile memory device

Patent metadata

Field	Value
Publication number	US-12456520-B2
Application number	US-202318382325-A
Country	US
Kind code	B2
Filing date	Oct 20, 2023
Priority date	Jan 12, 2023
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

A non-volatile memory device includes a memory cell array including memory cells coupled to word lines, a boost circuit that receives an external power supply voltage and generate a boosted voltage based on the external power supply voltage, a regulator that generates a regulated voltage based on the external power supply voltage, and a control logic that controls word line voltages provided to the word lines. The control logic performs plural program loops in a program operation for the memory cell array. The control logic provides an adjacent word line voltage to an adjacent word line that is adjacent to a selected word line. In a first section of the program loops, the control logic provides the regulated voltage as the adjacent word line voltage, and in a second section of the program loops, the control logic provides the boosted voltage as the adjacent word line voltage.

First claim

What is claimed is:

1. A non-volatile memory device comprising:
a memory cell array including memory cells coupled to a plurality of word lines;
a boost circuit configured to receive an external power supply voltage and generate a boosted voltage based on the external power supply voltage;
a regulator configured to generate a regulated voltage based on the external power supply voltage; and
a control logic configured to control word line voltages provided to the plurality of word lines,
wherein the control logic performs a plurality of program loops in a program operation for the memory cell array, and
wherein the control logic provides an adjacent word line voltage to at least one adjacent word line that is adjacent to a selected word line, and
wherein, in a first section of the plurality of program loops, the control logic provides the regulated voltage as the adjacent word line voltage, and in a second section of the plurality of program loops, the control logic provides the boosted voltage as the adjacent word line voltage.

2. The non-volatile memory device of claim 1 , further comprising a switch that receives the external power supply voltage and the boosted voltage,
wherein, in the first section, the switch outputs the external power supply voltage to the regulator, and the regulator regulates the external power supply voltage to generate the adjacent word line voltage,
wherein, in the second section, the switch outputs the boosted voltage to the regulator and the regulator regulates the boosted voltage to generate the adjacent word line voltage.

3. The non-volatile memory device of claim 1 , wherein the first section comprises initial program loops of the plurality of program loops, and the second section comprises subsequent remaining program loops of the plurality of program loops.

4. The non-volatile memory device of claim 1 , wherein the regulator comprises a first regulator and a second regulator,
wherein the first regulator provides a first regulating voltage to the at least one adjacent word line as the adjacent word line voltage,
wherein the second regulator provides a second regulating voltage to non-selected word lines among the plurality of word lines.

5. The non-volatile memory device of claim 1 , wherein an incremental step pulse programming (ISPP) voltage of which a level gradually increases as the plurality of program loops are performed is provided to the selected word line;
wherein a level of the adjacent word line voltage rises corresponding to a level rise of the ISPP voltage,
wherein the level of the adjacent word line voltage rises at least once in each of the first section and the second section.

6. The non-volatile memory device of claim 5 , further comprising a counter configured to count the plurality of program loops,
wherein, when a counting value of the counter is greater than or equal to a threshold value, the control logic provides the boosted voltage as the adjacent word line voltage.

7. The non-volatile memory device of claim 1 , wherein a level of the adjacent word line voltage increases stepwise at least once in a process of performing the plurality of program loops,
wherein the control logic provides the boosted voltage as the adjacent word line voltage to the at least one adjacent word line when the level of the adjacent word line voltage is greater than or equal to a threshold level.

8. The non-volatile memory device of claim 1 , wherein the control logic generates an adjustment code for adjusting a target level of the adjacent word line voltage and provides a control signal to switch from the regulated voltage as the adjacent word line voltage to the boosted voltage as the adjacent word line voltage based on the adjustment code.

9. The non-volatile memory device of claim 1 , wherein the external power supply voltage has a level between a minimum value and a maximum value of voltages to be provided to the at least one adjacent word line in the plurality of program loops.

10. The non-volatile memory device of claim 1 , further comprising a vertical flash memory device,
wherein the at least one adjacent word line comprises one or more word lines positioned above the selected word line and one or more word lines positioned below the selected word line.

11. The non-volatile memory device of claim 1 , wherein the memory cells are programmed to a plurality of threshold voltage states,
wherein, in a read operation or verify operation of the memory cells, the control logic provides the regulated voltage as the adjacent word line voltage in a read operation or verify operation for states having a relatively low threshold voltage level among the plurality of threshold voltage states, and the control logic provides the boosted voltage as the adjacent word line voltage in a read operation or verify operation for states having a relatively high threshold voltage level.

12. A method of operating a non-volatile memory device, in which a program operation of the non-volatile memory device comprises a plurality of program loops, the method comprises:
providing a first boosted voltage generated by boosting an external power supply voltage to a selected word line;
providing a first regulated voltage generated by regulating the external power supply voltage to a non-selected word line;
providing a second regulated voltage generated by regulating the external power supply voltage to at least one adjacent word line that is adjacent to the selected word line in initial loops of the plurality of program loops; and
providing a second boosted voltage generated by boosting the external power supply voltage to the at least one adjacent word line in subsequent loops after the initial loops are performed.

13. The method of claim 12 , wherein providing the second boosted voltage comprises providing a third regulated voltage generated by regulating the second boosted voltage to the at least one adjacent word line.

14. The method of claim 12 , wherein the external power supply voltage has a level between a minimum value and a maximum value of voltages provided to the at least one adjacent word line in the plurality of program loops.

15. The method of claim 12 , wherein, while the plurality of program loops are successively executed, a level of a voltage provided to the at least one adjacent word line gradually increases,
wherein the initial loops comprise program loops executed when the level of the voltage less than a threshold level, and the subsequent loops comprise program loops executed when the level of the voltage is greater than or equal to the threshold level.

16. The method of claim 12 , wherein memory cells are programmed to a plurality of threshold voltage states,
wherein the method further comprises:
providing the second regulated voltage to the at least one adjacent word line, during a read operation for states having a relatively low threshold voltage level among the plurality of threshold voltage states; and
providing the second boosted voltage to the at least one adjacent word line, during a read operation for states having a relatively high threshold voltage level among the plurality of threshold voltage states.

17. A storage device comprising:
a non-volatile memory having a memory cell array including memory cells connected to a plurality of word lines;
a controller configured to control a memory operation of the non-volatile memory; and
a power management integrated circuit (PMIC) configured to provide a high voltage to the non-volatile memory,
wherein the non-volatile memory comprises:
a regulator configur

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoon Jayang
• Kim Chihyun
• Park Sangsoo
• Park Junehong
• Yoon Chiweon
• Choi Hyeongdo

Classifications

• G11C16/30 Primary

  Power supply circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title