Explicit lockstep for functional safety

Patent metadata

Field	Value
Publication number	US-12455799-B2
Application number	US-202318494565-A
Country	US
Kind code	B2
Filing date	Oct 25, 2023
Priority date	Jun 16, 2023
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

A method of explicit lockstep for functional safety includes spawning, by a main thread, a first safe thread core and a second safe thread core. The method also includes initializing and mapping a first data register associated with the first safe thread core to each safe variable of a set of predetermined safe variables. The method further includes initializing and mapping a second data register associated with the second safe thread core to each safe variable of the set of predetermined safe variables. The method also includes comparing, by a hardware comparator, a first safe variable value in the first data register to a second safe variable value in the second register. The method further includes issuing an error completion to the first safe thread core and the second safe thread core when the hardware comparator detects a mismatch between the first data register and the second data register.

First claim

What is claimed is:

1. A method of explicit lockstep for functional safety, the method comprising:
spawning, by a main thread, a first safe thread and a second safe thread;
initializing and mapping a first data register associated with the first safe thread to each safe variable of a set of predetermined safe variables;
allocating, by the main thread, a first physical memory page and a first address space mapped to the first data register associated with the first safe thread;
initializing and mapping a second data register associated with the second safe thread to each safe variable of the set of predetermined safe variables;
allocating, by the main thread, a second physical memory page and a second address space mapped to the second data register associated with the second safe thread;
comparing, by a hardware comparator, a first safe variable value in the first data register to a second safe variable value in the second register; and
issuing an error completion to the first safe thread and the second safe thread when the hardware comparator detects a mismatch between the first data register and the second data register.

2. The method of claim 1 , further comprising allowing a read to an address associated with the first safe variable value when the hardware comparator detects a match.

3. The method of claim 1 , further comprising blocking the first safe thread or the second safe thread from proceeding until both the first data register and the second data register are written with the first safe variable value.

4. The method of claim 1 , further comprising stalling a read of the first safe thread and the second safe thread until both the first safe thread and the second safe thread write identical values to the first data register and the second data register.

5. The method of claim 1 , further comprising stalling the first safe thread or the second safe thread until both the first safe thread and the second safe thread are at a synchronization point.

6. The method of claim 1 , in which one of the first safe thread or the second safe thread executes on a processor core of the main thread.

7. The method of claim 1 , further comprising blocking a read by any of the first safe thread and the second safe thread when the hardware comparator detects the mismatch between the first data register and the second data register.

8. The method of claim 1 , further comprising writing the first safe variable value to memory when a match is detected between the first data register and the second data register.

9. The method of claim 1 , further comprising issuing a hardware interrupt when the hardware comparator detects the mismatch between the first register and the second register.

10. A non-transitory computer-readable medium having program code recorded thereon for explicit lockstep for functional safety, the program code being executed by a processor and comprising:
program code to spawn, by a main thread, a first safe thread and a second safe thread;
program code to initialize and map a first data register associated with the first safe thread to each safe variable of a set of predetermined safe variables;
program code to allocate, by the main thread, a first physical memory page and a first address space mapped to the first data register associated with the first safe thread;
program code to initialize and map a second data register associated with the second safe thread to each safe variable of the set of predetermined safe variables;
program code to allocate, by the main thread, a second physical memory page and a second address space mapped to the second data register associated with the second safe thread;
program code to compare, by a hardware comparator, a first safe variable value in the first data register to a second safe variable value in the second register; and
program code to issue an error completion to the first safe thread and the second safe thread when the hardware comparator detects a mismatch between the first data register and the second data register.

11. The non-transitory computer-readable medium of claim 10 , further comprising program code to allow a read to an address associated with the first safe variable value when the hardware comparator detects a match.

12. The non-transitory computer-readable medium of claim 10 , further comprising program code to block the first safe thread or the second safe thread from proceeding until both the first data register and the second data register are written with the first safe variable value.

13. The non-transitory computer-readable medium of claim 10 , further comprising program code to stall a read of the first safe thread and the second safe thread until both the first safe thread and the second safe thread write identical values to the first data register and the second data register.

14. The non-transitory computer-readable medium of claim 10 , further comprising program code to stall the first safe thread or the second safe thread until both the first safe thread and the second safe thread are at a synchronization point.

15. The non-transitory computer-readable medium of claim 10 , in which one of the first safe thread or the second safe thread executes on a processor core of the main thread.

16. The non-transitory computer-readable medium of claim 10 , further comprising program code to block a read by any of the first safe thread and the second safe thread when the hardware comparator detects the mismatch between the first data register and the second data register.

17. The non-transitory computer-readable medium of claim 10 , further comprising program code to write the first safe variable value to memory when a match is detected between the first data register and the second data register.

18. The non-transitory computer-readable medium of claim 10 , further comprising program code to issue a hardware interrupt when the hardware comparator detects the mismatch between the first register and the second register.

Assignees

• Qualcomm Inc

Inventors

• Stracovsky Henry
• Maor Nir
• Priore Antonio
• Sinha Vikas Kumar
• Kitchin Paul
• Oak Sunil

Classifications

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06F11/1641

  where the comparison is not performed by the redundant processing components · CPC title

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title

• G06F11/1629 Primary

  Error detection by comparing the output of redundant processing systems · CPC title