Storage device for executing background operation based on power state and operating method thereof

Patent metadata

Field	Value
Publication number	US-12455607-B2
Application number	US-202318172477-A
Country	US
Kind code	B2
Filing date	Feb 22, 2023
Priority date	Nov 25, 2022
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

A storage device may enter a plurality of intermediate power states sequentially while entering from a first power state to a second power state. The storage device may check background flag information while entering each of the plurality of intermediate power states, and execute a target background operation, executable in a first intermediate power state, based on the background flag information.

First claim

What is claimed is:

1. A storage device comprising:
a memory including a plurality of memory blocks; and
a controller configured to:
during changing a power state of the controller from a first power state to a second power state, change the power state of the controller through a plurality of intermediate power states between the first power state and the second power state,
determine background operations executable in each of the plurality of intermediate power states when the power state of the controller changes to each of the plurality of intermediate power states, and
execute a target background operation, among the executable background operations executable in a first intermediate power when the power state of the controller changes to the first intermediate power state,
wherein the controller is configured to determine the target background operation to execute a background operation having a higher priority earlier,
wherein the controller is configured to execute the target background operation for less than a set threshold execution time, and
wherein the controller is configured to suspend the target background operation when the target background operation is not completed after the threshold execution time elapses after starting the target background operation.

2. The storage device according to claim 1 ,
wherein the controller is configured to decrease an operating clock and an operating voltage when changing a second intermediate power state from the first intermediate power state.

3. The storage device according to claim 1 ,
wherein the background operations include at least one of a garbage collection on the plurality of memory blocks; flushing data stored in a buffer to the memory; migrating data stored in a first type memory block, among the plurality of memory blocks, to a second type memory block having a larger storage capacity than the first type memory block; and erasing one or more of the plurality of memory blocks.

4. The storage device according to claim 1 ,
wherein the controller is configured to execute the target background operation executable in a first intermediate power state before entering a second intermediate power state.

5. The storage device according to claim 1 ,
wherein the controller is configured to set the priority of the garbage collection operation to be inversely proportional to the number of free memory blocks included in the memory or to be proportional to the size of invalid data stored in the memory.

6. The storage device according to claim 1 ,
wherein the controller is configured to set the priority of the operation migrating data from the first type memory block to the second type memory block to be inversely proportional to the size of the data to be migrated from the first type memory block to the second type memory block.

7. The storage device according to claim 1 ,
wherein the controller is configured to set the priority of the operation flushing the data stored in the buffer to the memory to be inversely proportional to the size of the data stored in the buffer.

8. The storage device according to claim 1 ,
wherein the controller is further configured to check whether an event instructing to return to the first power state is set in the first intermediate power state.

9. The storage device according to claim 1 ,
wherein the controller is configured to determine the background operations executable in each of the plurality of intermediate power states by background flag information.

10. A method for operating a storage device, comprising:
during changing a power state from a first power state to a second power state, change the power state through a first intermediate power state among a plurality of intermediate power states between the first power state and the second power state;
determining background operations executable in each of the plurality of intermediate power states when the power state changes to each of the plurality of intermediate power states; and
executing a target background operation among the executable background operations executable in a first intermediate power state, when the power state of the controller changes to the first intermediate power state,
wherein the executing the target background operation determines the target background operation to execute a background operation having a higher priority earlier,
wherein the executing the target background operation executes the target background operation for less than a set threshold execution time, and
wherein the executing the target background operation executes suspends the target background operation when the target background operation is not completed after the threshold execution time elapses after starting the target background operation.

11. The method according to claim 10 , further comprising:
decreasing an operating clock and an operating voltage when changing a second intermediate power state from the first intermediate power state.

12. The method according to claim 10 ,
wherein the background operations include at least one of a garbage collection on the plurality of memory blocks; flushing data stored in a buffer to the memory; migrating data stored in a first type memory block among the plurality of memory blocks to a second type memory block having a larger storage capacity than the first type memory block; and erasing one or more of the plurality of memory blocks.

13. The method according to claim 10 ,
wherein the executing the target background operation executes the target background operation executable in a first intermediate power state before entering a second intermediate power state.

14. The method according to claim 10 ,
wherein the priority of the garbage collection operation is set to be inversely proportional to the number of free memory blocks included in the memory or to be proportional to the size of invalid data stored in the memory.

15. The method according to claim 10 ,
wherein the priority of the operation migrating data from the first type memory block to the second type memory block is set to be inversely proportional to the size of the data to be migrated from the first type memory block to the second type memory block.

16. The method according to claim 10 ,
wherein the priority of the operation flushing the data stored in the buffer to the memory is set to be inversely proportional to the size of the data stored in the buffer.

17. The method according to claim 10 ,
wherein the determining background operations determines the background operations executable in each of the plurality of intermediate power states by background flag information.

18. A controller comprising:
a memory interface capable of communicating with a memory including a plurality of memory blocks; and
a control circuit configured to:
during changing a power state of the controller from a first power state to a second power state, change the power state of the controller through a plurality of intermediate power states between a normal state consuming a first power and a low power state consuming a second power, which is less than the first power, and
execute, while entering each of the plurality of intermediate power states, an executable background operation from among a plurality of background operations,
wherein the control circuit is configured to determine target background operation to execute a background operation having a higher priority earlier,
wherein the control circuit is configured to execute the executable background operation for less than

Assignees

• Sk Hynix Inc

Inventors

• Jang In Jong

Classifications

• G06F1/3296 Primary

  by lowering the supply or operating voltage · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F12/0253

  Garbage collection, i.e. reclamation of unreferenced memory · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title