Controller executing activation mode or low power mode based on state of multiple sub-circuits and operating method thereof

Patent metadata

Field	Value
Publication number	US-12455606-B2
Application number	US-202217659160-A
Country	US
Kind code	B2
Filing date	Apr 13, 2022
Priority date	Dec 21, 2021
Publication date	Oct 28, 2025
Grant date	Oct 28, 2025

Abstract

Embodiments of the present disclosure relate to a controller and operation method thereof. According to embodiments of the present disclosure, the controller may include i) a plurality of sub-circuits and ii) a processor configured to: determine the state of the plurality of sub-circuits, determine whether activation conditions corresponding to the plurality of sub-circuits are satisfied at a first time point, and control the controller to operate in an activation mode or in a low-power mode at a second time point, depending on whether the activation conditions corresponding to the plurality of sub-circuits are satisfied.

First claim

What is claimed is:

1. A controller comprising:
a plurality of sub-circuits; and
a processor configured to:
control the controller to operate in an activation mode for the controller using a current with a current value greater than or equal to an activation current, in response to receiving a command from outside;
determine whether activation conditions of the plurality of sub-circuits are satisfied during the activation mode, each of the activation conditions indicating whether a corresponding sub-circuit requires a current with a current value greater than or equal to the activation current; and
control the controller to operate in a low-power mode for the controller using a current with a current value lower than the activation current value, when the activation conditions of all of the plurality of sub-circuits are not satisfied and a predetermined time has elapsed from an initiation of the activation mode.

2. The controller of claim 1 ,
wherein the processor is configured to determine whether activation conditions of the plurality of sub-circuits are satisfied at a first time point,
wherein the processor is configured to control the controller to operate in the activation mode or in the low-power mode at a second time point,
wherein the second time point is a time point after a predetermined time has elapsed from when a current greater than or equal to the activation current value is used to process a command received from outside the controller,
wherein the first time point is the time point when a predetermined time elapses after the controller receives the command from the outside of the controller, and
wherein the second time point is determined according to information of the command.

3. The controller of claim 2 ,
wherein one of the plurality of sub-circuits is a processing unit capable of executing logical operation, and
wherein the processor is operable to determine that an activation condition for the processing unit is satisfied when the processing unit is executing a logical operation at the first time point.

4. The controller of claim 3 ,
wherein the logical operation is for transmitting an external command or data received from outside of the controller to the processor.

5. The controller of claim 2 ,
wherein one of the plurality of sub-circuits is a sequential read information circuit that is operable to store information on a logical address area for which the command has requested a sequential read operation, and
wherein the processor is operable to determine that an activation condition for the sequential read information circuit is satisfied when the sequential read operation for the logical address area is being executed at the first time point.

6. The controller of claim 2 ,
wherein one of the plurality of sub-circuits is a vector search circuit that is operable to search for a physical address mapped to a logical address corresponding to the command, and
wherein the processor is operable to determine that an activation condition for the vector search circuit is satisfied when the vector search circuit is searching for a physical address for a specific logical address at the first time point.

7. The controller of claim 2 ,
wherein one of the plurality of sub-circuits is a mapping table search circuit that is operable to search for a map cache entry corresponding to a specific logical address in a map cache that caches map cache entries containing mapping information between logical and physical addresses, and
wherein the processor is operable to determine that an activation condition for the mapping table search circuit is satisfied when the mapping table search circuit is searching the map cache for the map cache entry corresponding to the specific logical address at the first time point.

8. The controller of claim 2 ,
wherein one of the plurality of sub-circuits is a command queue storage circuit operable to store a command queue for queuing commands received from outside the controller, and
wherein the processor is operable to determine that an activation condition for the command queue storage circuit is satisfied when at least one command, other than a command for instructing an operation executed in an idle state, is queued in the command queue at the first time point.

9. The controller of claim 2 ,
wherein one of the plurality of sub-circuits is a buffer storage circuit having a buffer that stores read data or write data, and
wherein the processor is operable to determine that an activation condition for the buffer storage circuit is satisfied when read data or write data is stored in the buffer at the first time point.

10. A method for operating a controller, comprising:
controlling the controller to operate in an activation mode for the controller using a current with a current value greater than or equal to an activation current, in response to receiving a command from outside;
determining whether activation conditions of the plurality of sub-circuits are satisfied during the activation mode, each of the activation conditions indicating whether a corresponding sub-circuit requires a current with a current value greater than or equal to the activation current;
and
controlling the controller to operate in a low-power mode for the controller using a current with a current value lower than the activation current value, when the activation conditions of all of the plurality of sub-circuits are not satisfied and a predetermined time has elapsed from an initiation of the activation mode.

11. The method according to claim 10 ,
wherein activation conditions of the plurality of sub-circuits are satisfied is determined at a first time point,
whether controlling the controller to operate in the activation mode or in the low-power mode at a second time point,
wherein the second time point is a time point after a predetermined time has elapsed from when a current greater than or equal to the activation current value is used to process a command received from outside the controller,
wherein the first time point is the time point when a predetermined time elapses after the controller receives the command from the outside of the controller, and
wherein the second time point is determined according to information of the command.

12. The method according to claim 10 ,
wherein one of the plurality of sub-circuits is a processing unit capable of executing logical operation, and
wherein an activation condition for the processing unit is satisfied when the processing unit is executing a logical operation at the first time point.

13. The method according to claim 10 ,
wherein the logical operation is for transmission of an external command or data received from outside of the controller.

14. The method according to claim 10 ,
wherein one of the plurality of sub-circuits is a sequential read information circuit operable to store information on the logical address area for which the command has requested a sequential read, and
wherein an activation condition for the sequential read information circuit is satisfied when the sequential read operation for the logical address area is being executed at the first time point.

15. The method according to claim 10 ,
wherein one of the plurality of sub-circuits is a vector search circuit operable to search for a physical address mapped to a logical address corresponding to the command, and
wherein an activation condition for the vector search circuit is satisfied when the vector search circuit is searching for a physical address for a specific logical address at the first time point.

16

Assignees

• Sk Hynix Inc

Inventors

• Jang In Jong

Classifications

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F1/3206 Primary

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/3275

  Power saving in memory, e.g. RAM, cache · CPC title

• G06F1/3293

  by switching to a less power-consuming processor, e.g. sub-CPU · CPC title