Display panel having a fan-out region and display device

Patent metadata

Field	Value
Publication number	US-12453258-B2
Application number	US-202117789852-A
Country	US
Kind code	B2
Filing date	Jun 22, 2021
Priority date	Jun 22, 2021
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

A display panel has a display region, a fan-out region located on a side of the display region, and a bonding region located on a side of the fan-out region away from the display region. The display panel includes a gate driving circuit disposed in the display region, a plurality of data lines and a plurality of control signal lines that all extends from the display region to the fan-out region, and a plurality of data fan-out leads and a plurality of first fan-out leads that are all disposed in the fan-out region. Each data line is electrically connected to a data fan-out lead. The data fan-out leads are gathered to the bonding region. The control signal lines are electrically connected to the gate driving circuit. Each control signal line is electrically connected to a first fan-out lead. The first fan-out leads are gathered to the bonding region.

First claim

What is claimed is:

1. A display panel having a display region, a fan-out region located on a side of the display region, a bonding region located on a side of the fan-out region away from the display region, and a peripheral region surrounding the display region, wherein the peripheral region includes a first sub-peripheral region, a second sub-peripheral region, a third sub-peripheral region and a fourth sub-peripheral region; the first sub-peripheral region and the second sub-peripheral region are respectively located on two opposite sides of the display region in a first direction, the third sub-peripheral region and the fourth sub-peripheral region are respectively located on two opposite sides of the display region in a second direction, and the first direction is substantially perpendicular to the second direction; and the fan-out region and the bonding region are located in the fourth sub-peripheral region;
the display panel comprising:
a plurality of data lines extending from the display region to the fan-out region;
a plurality of data fan-out leads disposed in the fan-out region; wherein each data line is electrically connected to a data fan-out lead; and the plurality of data fan-out leads are gathered to the bonding region;
a gate driving circuit disposed in the display region;
a plurality of control signal lines electrically connected to the gate driving circuit and configured to transmit respective control signals to the gate driving circuit; wherein the plurality of control signal lines extend from the display region to the fan-out region; and
a plurality of first fan-out leads disposed in the fan-out region; wherein each control signal line is electrically connected to a first fan-out lead; and the plurality of first fan-out leads are gathered to the bonding region; wherein
the control signal line includes a first line segment and a second line segment that are electrically connected to each other;
of first line segments of the plurality of control signal lines, some first line segments extend from the third sub-peripheral region, along the first sub-peripheral region, to the fan-out region;
some other first line segments extend from the third sub-peripheral region, along the second sub-peripheral region, to the fan-out region;
second line segments of the plurality of control signal lines extend from the display region to the third sub-peripheral region; and
an end of the first line segment is electrically connected to an end of the second line segment extending to the third sub-peripheral region, and another end of the first line segment is electrically connected to the first fan-out lead.

2. The display panel according to claim 1 , wherein an end of the control signal line extending to the fan-out region is electrically connected to the first fan-out lead.

3. The display panel according to claim 2 , further comprising:
a supply voltage bus disposed in the fan-out region and extending in the first direction; the first direction being substantially perpendicular to a direction from the display region to the fan-out region; wherein
the plurality of first fan-out leads and the supply voltage bus are made of a same material and arranged in a same layer, and the first fan-out lead bypasses one of two opposite sides of the supply voltage bus in the first direction, and extends to a side of the supply voltage bus away from the display region.

4. The display panel according to claim 3 , further comprising:
a plurality of connection lines disposed between the supply voltage bus and the display region and extending in the first direction; the control signal line being electrically connected to the first fan-out lead through a connection line of the plurality of connection lines.

5. The display panel according to claim 4 , wherein the display panel comprises:
a gate conductive layer, the plurality of first fan-out leads, the plurality of connection lines and the supply voltage bus being disposed in the gate conductive layer; and a source-drain conductive layer disposed on a side of the gate conductive layer away from a substrate of the display panel, the plurality of control signal lines, the plurality of data lines and the plurality of data fan-out leads being disposed in the source-drain conductive layer; or
a gate conductive layer, the plurality of first fan-out leads, the plurality of connection lines and the supply voltage bus being disposed in the gate conductive layer; a source-drain conductive layer disposed on a side of the gate conductive layer away from a substrate of the display panel, the plurality of control signal lines, the plurality of data lines and the plurality of data fan-out leads being disposed in the source-drain conductive layer; and a first insulating layer disposed between the gate conductive layer and the source-drain conductive layer, the first insulating layer being provided with first vias therein; wherein the control signal line is electrically connected to the connection line through a first via of the first vias.

6. The display panel according to claim 5 , wherein orthographic projections of the plurality of first fan-out leads on the substrate are staggered from orthographic projections of the plurality of data fan-out leads on the substrate.

7. The display panel according to claim 2 , further comprising:
a supply voltage bus disposed in the fan-out region and extending in the first direction; the first direction being substantially perpendicular to a direction from the display region to the fan-out region; wherein
at least a portion of the first fan-out lead is arranged in a different layer from the supply voltage bus and the data fan-out leads; and
an orthographic projection of the first fan-out lead on a substrate of the display panel is partially overlapped with an orthographic projection of the supply voltage bus on the substrate.

8. The display panel according to claim 7 , wherein the first fan-out lead includes a first lead segment and a second lead segment that are electrically connected to each other; wherein
the control signal line is electrically connected to an end of the first lead segment away from the second lead segment; and
an end of the second lead segment away from the first lead segment extends to the bonding region.

9. The display panel according to claim 8 , wherein at least one first lead segment includes a first sub-lead segment and a second sub-lead segment that are electrically connected to each other; wherein
the first sub-lead segment extends in the first direction; and
the second sub-lead segment extends in the second direction.

10. The display panel according to claim 8 , wherein the display panel comprises:
a gate conductive layer, the supply voltage bus being disposed in the gate conductive layer;
a source-drain conductive layer disposed on a side of the gate conductive layer away from the substrate, the plurality of control signal lines, the plurality of data lines and the plurality of data fan-out leads being disposed in the source-drain conductive layer; and
an electrode layer disposed on a side of the source-drain conductive layer away from the substrate;
wherein the first lead segment is disposed in the electrode layer, and the second lead segment is disposed in the source-drain conductive layer or the gate conductive layer;
an orthographic projection of the first lead segment on the substrate is partially overlapped with the orthographic projection of the supply voltage bus on the substrate, and is partially overlapped with the orthographic projection of the at least one data fan-out lead on the substrate; and
an orthographic projection of the second lead segment on the substrate is staggered from orthograph

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Han Ying
• Lin Yicheng
• Xu Pan
• Wang Guoying
• Zhang Xing
• Gao Zhan
• Chu Mingi

Classifications

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10D86/00

  Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates · CPC title

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title

• G09G3/36

  using liquid crystals · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title