Display panel, method for manufacturing display panel, and display device

Patent metadata

Field	Value
Publication number	US-12453254-B2
Application number	US-202217816406-A
Country	US
Kind code	B2
Filing date	Jul 30, 2022
Priority date	Jun 30, 2022
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

The present application provides a display panel, a method for manufacturing the display panel, and a display device, including: a substrate; a pixel driving circuit layer located on the substrate, comprising a pixel driving circuit; an auxiliary conductive portion disposed on the substrate; a passivation layer comprising a first passivation layer and a second passivation layer, the first passivation layer formed on the pixel driving circuit layer and the auxiliary conductive portion, and the second passivation layer formed on the first passivation layer so that the second passivation layer and the first passivation layer together define an undercut opening; a first electrode formed on the passivation layer, and electrically connected to the pixel driving circuit; a second electrode formed on the first electrode; the second electrode is connected in parallel with the auxiliary conductive portion through the undercut opening.

First claim

What is claimed is:

1. A display panel, comprising:
a substrate;
a pixel driving circuit layer, located on the substrate, comprising a pixel driving circuit;
an auxiliary conductive portion, disposed on the substrate;
a passivation layer, comprising a first passivation layer and a second passivation layer, the first passivation layer being formed on the pixel driving circuit layer and the auxiliary conductive portion, and the second passivation layer being formed on the first passivation layer so that the second passivation layer and the first passivation layer together define an undercut opening;
a first electrode, formed on the passivation layer, and electrically connected to the pixel driving circuit;
a second electrode, formed on the first electrode, the auxiliary conductive portion being configured to electrically connect to a VSS signal line providing a voltage signal for the second electrode; and
a common layer, located between the first electrode and the second electrode;
wherein the common layer is disconnected in the undercut opening, and the second electrode is connected in parallel with the auxiliary conductive portion through the undercut opening.

2. The display panel as claimed in claim 1 , wherein an etching rate of the second passivation layer is less than an etching rate of the first passivation layer under same etching conditions.

3. The display panel as claimed in claim 2 , wherein an etching rate ratio of the first passivation layer to the second passivation layer is greater than or equal to 10.

4. The display panel as claimed in claim 2 , wherein a material of the first passivation layer is SiO x , and a material of the second passivation layer is SiN x .

5. The display panel as claimed in claim 4 , wherein the passivation layer further comprises a third passivation layer, the third passivation layer is formed on the second passivation layer, and the material of the first passivation layer is same as a material of the third passivation layer.

6. The display panel as claimed in claim 1 , wherein the pixel driving circuit layer further comprises a first conductive layer, the pixel driving circuit comprises a TFT, and the first conductive layer comprises a source electrode and a drain electrode of the TFT arranged in a same layer, and the auxiliary conductive portion.

7. The display panel as claimed in claim 6 , wherein the pixel driving circuit layer further comprises a light-shielding layer, and the light-shielding layer comprises a light-shielding portion and a conductive line arranged in a same layer, the light-shielding portion is located between an active pattern of the TFT and the substrate and at least partially overlaps with the active pattern, and the conductive line is electrically connected to the auxiliary conductive portion.

8. A method for manufacturing a display panel, comprising:
forming a pixel driving circuit layer on a substrate, the pixel driving circuit layer comprising a pixel driving circuit;
forming an auxiliary conductive portion on the substrate;
forming a passivation layer, the passivation layer comprising a first passivation layer and a second passivation layer, the first passivation layer being formed on the pixel driving circuit layer and the auxiliary conductive portion, and the second passivation layer being formed on the first passivation layer;
patterning the first passivation layer and the second passivation layer so that the second passivation layer and the first passivation layer together define an undercut opening;
forming a first electrode on the passivation layer, the first electrode electrically being connected to the pixel driving circuit;
forming a common layer on the first electrode, the common layer being disconnected in the undercut opening; and
forming a second electrode on the common layer, the second electrode being connected in parallel with the auxiliary conductive portion through the undercut opening, and the auxiliary conductive portion being configured to electrically connect to a VSS signal line providing a voltage signal for the second electrode.

9. The method for manufacturing the display panel as claimed in claim 8 , wherein the step of patterning the first passivation layer and the second passivation layer comprises:
patterning the first passivation layer and the second passivation layer, so that the second passivation layer and the first passivation layer together define a connection opening;
forming a planarization layer on the first passivation layer and the second passivation layer; and
patterning the planarization layer, the first passivation layer, and the second passivation layer;
wherein an etching rate of the second passivation layer under a condition of hydrofluoric acid solution is less than an etching rate of the first passivation layer under the condition of hydrofluoric acid solution, so that the second passivation layer and the first passivation layer together define the undercut opening.

10. The method for manufacturing the display panel as claimed in claim 9 , wherein an etching rate ratio of the first passivation layer to the second passivation layer is greater than or equal to 10.

11. The method for manufacturing the display panel as claimed in claim 9 , wherein a material of the first passivation layer is SiO x , and a material of the second passivation layer is SiN x .

12. The method for manufacturing the display panel as claimed in claim 8 , wherein the pixel driving circuit layer further comprises a first conductive layer, the pixel driving circuit comprises a TFT, and the first conductive layer comprises a source electrode and a drain electrode of the TFT arranged in a same layer, and the auxiliary conductive portion.

13. The method for manufacturing the display panel as claimed in claim 12 , wherein the pixel driving circuit layer further comprises a light-shielding layer, and the light-shielding layer comprises a light-shielding portion and a conductive line arranged in a same layer, the light-shielding portion is located between an active pattern of the TFT and the substrate and at least partially overlaps with the active pattern, and the conductive line is electrically connected to the auxiliary conductive portion.

14. A display device, comprising a display panel, and the display panel comprising:
a substrate;
a pixel driving circuit layer, located on the substrate, comprising a pixel driving circuit;
an auxiliary conductive portion, disposed on the substrate;
a passivation layer, comprising a first passivation layer and a second passivation layer, the first passivation layer being formed on the pixel driving circuit layer and the auxiliary conductive portion, and the second passivation layer being formed on the first passivation layer so that the second passivation layer and the first passivation layer together define an undercut opening;
a first electrode, formed on the passivation layer, and electrically connected to the pixel driving circuit;
a second electrode, formed on the first electrode, the auxiliary conductive portion being configured to electrically connect to a VSS signal line providing a voltage signal for the second electrode; and
a common layer, located between the first electrode and the second electrode;
wherein the common layer is disconnected in the undercut opening, and the second electrode is connected in parallel with the auxiliary conductive portion through the undercut opening.

15. The display device as claimed in claim 14 , wherein an etching rate of the second passivation layer is less than an etching rate of the first passivation layer under same etching condi

Assignees

• Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Zhou Libin

Classifications

• H10K59/126

  Shielding, e.g. light-blocking means over the TFTs · CPC title

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K71/20

  Changing the shape of the active layer in the devices, e.g. patterning · CPC title