Silicon carbide metal oxide semiconductor field effect transistor and manufacturing method of silicon carbide metal oxide semiconductor field effect transistor

Patent metadata

Field	Value
Publication number	US-12453167-B2
Application number	US-202118248002-A
Country	US
Kind code	B2
Filing date	Jul 30, 2021
Priority date	Oct 19, 2020
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

Some embodiments of the present disclosure provide a silicon carbide metal oxide semiconductor field effect transistor and a manufacturing method. The transistor includes first and second cells which jointly include a drain electrode layer, an ohmic contact layer, a substrate layer, an epitaxial layer, an interlayer dielectric layer, and a source electrode layer, the first cell further includes a first deep well region, a second deep well region, a first shallow well region, a second shallow well region, a two first source region, a two second source region, a first gate oxide layer, and a first polysilicon gate, and the second cell further includes a third deep well region, a fourth deep well region, a third shallow well region, a fourth shallow well region, a second gate oxide layer, a third gate oxide layer, a second polysilicon gate, and a third polysilicon gate.

First claim

What is claimed is:

1. A silicon carbide metal oxide semiconductor field effect transistor, comprising a first cell and a second cell that are disposed alternately, wherein the first cell and the second cell jointly comprises a drain electrode layer, an ohmic contact layer, a substrate layer, an epitaxial layer, an interlayer dielectric layer, and a source electrode layer which are disposed in a stacking mode, wherein
the first cell further comprises: a first deep well region and a second deep well region which are formed in the epitaxial layer and connected with the interlayer dielectric layer;
a first shallow well region and a second shallow well region which are formed in the first deep well region and the second deep well region, respectively;
two first source region and two second source region which are formed in the first deep well region and the second deep well region, respectively; wherein the two first source region are symmetric relative to the first shallow well region and are connected with the first shallow well region; and the two second source region are symmetric relative to the second shallow well region and are connected with the second shallow well region;
a first gate oxide layer, which is formed in the interlayer dielectric layer and connected with the epitaxial layer, the first deep well region and the second deep well region; and
a first polysilicon gate, which is also formed in the interlayer dielectric layer and covers the first gate oxide layer;
the second cell comprises: a third deep well region and a fourth deep well region which are formed in the epitaxial layer and connected with the interlayer dielectric layer;
a third shallow well region and a fourth shallow well region which are formed in the third deep well region and the fourth deep well region respectively;
a second gate oxide layer and a third gate oxide layer which are formed in the interlayer dielectric layer and cover the third deep well region and the fourth deep well region respectively; and
a second polysilicon gate and a third polysilicon gate which are formed in the interlayer dielectric layer and cover the second gate oxide layer and the third gate oxide layer respectively;
wherein the source electrode layer comprises a first settling part in ohmic contact with the first shallow well region and the two first source region, a second settling part in ohmic contact with the second shallow well region and the two second source region, a third settling part in ohmic contact with the third shallow well region, a fourth settling part in Schottky contact with the third deep well region, the fourth deep well region and the epitaxial layer, and a fifth settling part in ohmic contact with the fourth shallow well region, and an interval between the third deep well region and the fourth deep well region is smaller than an interval between the first deep well region and the second deep well region.

2. The silicon carbide metal oxide semiconductor field effect transistor as claimed in claim 1 , wherein the interval between the third deep well region and the fourth deep well region is 1.0-3.0 μm.

3. The silicon carbide metal oxide semiconductor field effect transistor as claimed in claim 1 , wherein an ohmic contact between the first settling part and the first shallow well region, an ohmic contact between the first settling part and the two first source region, an ohmic contact between the second settling part and the second shallow well region, an ohmic contact between the second settling part and the two second source region, an ohmic contact between the third settling part and the third shallow well region, an ohmic contact between the fifth settling part and the fourth shallow well region are all formed by aluminum and titanium, and thicknesses of the ohmic contact between the first settling part and the first shallow well region, the ohmic contact between the first settling part and the two first source region, the ohmic contact between the second settling part and the second shallow well region, the ohmic contact between the second settling part and the two second source region, the ohmic contact between the third settling part and the third shallow well region, the ohmic contact between the fifth settling part and the fourth shallow well region are all 10-500 nm.

4. The silicon carbide metal oxide semiconductor field effect transistor as claimed in claim 1 , wherein an ohmic contact between the first settling part and the first shallow well region, an ohmic contact between the first settling part and the two first source region, an ohmic contact between the second settling part and the second shallow well region, an ohmic contact between the second settling part and the two second source region, an ohmic contact between the third settling part and the third shallow well region, an ohmic contact between the fifth settling part and the fourth shallow well region are all formed by aluminum and nickel, and thicknesses of the ohmic contact between the first settling part and the first shallow well region, the ohmic contact between the first settling part and the two first source region, the ohmic contact between the second settling part and the second shallow well region, the ohmic contact between the second settling part and the two second source region, the ohmic contact between the third settling part and the third shallow well region, the ohmic contact between the fifth settling part and the fourth shallow well region are all 10-500 nm.

5. The silicon carbide metal oxide semiconductor field effect transistor as claimed in claim 1 , wherein an ohmic contact between the first settling part and the first shallow well region, an ohmic contact between the first settling part and the two first source region, an ohmic contact between the second settling part and the second shallow well region, an ohmic contact between the second settling part and the two second source region, an ohmic contact between the third settling part and the third shallow well region, an ohmic contact between the fifth settling part and the fourth shallow well region are all formed by aluminum, titanium and nickel, and thicknesses of the ohmic contact between the first settling part and the first shallow well region, the ohmic contact between the first settling part and the two first source region, the ohmic contact between the second settling part and the second shallow well region, the ohmic contact between the second settling part and the two second source region, the ohmic contact between the third settling part and the third shallow well region, the ohmic contact between the fifth settling part and the fourth shallow well region are all 10-500 nm.

6. The silicon carbide metal oxide semiconductor field effect transistor as claimed in claim 1 , wherein a Schottky contact between the fourth settling part and the third deep well region, a Schottky contact between the fourth settling part and the fourth deep well region, a Schottky contact between the fourth settling part and the epitaxial layer are all formed by titanium, molybdenum, tungsten and nickel, and thicknesses of the Schottky contact between the fourth settling part and the third deep well region, the Schottky contact between the fourth settling part and the fourth deep well region, the Schottky contact between the fourth settling part and the epitaxial layer are all 10-500 nm.

7. The silicon carbide metal oxide semiconductor field effect transistor as claimed in claim 1 , wherein a Schottky contact between the fourth settling part and the third deep well region, a Schottky contact between the fourth settling part and the fourth deep well region, a Schottky contact between the fourth settling part and the epitaxial layer are all formed by titanium, molybdenum, tungsten and p

Assignees

• Gree Electric Appliances Inc Zhuhai
• Edgeless Semiconductor Co Ltd Of Zhuhai

Inventors

• Chen Daokun
• Shi Bo
• Lin Yiren
• Zeng Dan

Classifications

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D12/031

  of IGBTs · CPC title

• H10D30/0291

  of vertical DMOS [VDMOS] FETs · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title