Voltage regulator comprising a charge pump circuit

Patent metadata

Field	Value
Publication number	US-12451803-B2
Application number	US-202318162870-A
Country	US
Kind code	B2
Filing date	Feb 1, 2023
Priority date	Feb 15, 2022
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

In embodiments, a voltage regulator has an input node to receive an input voltage and an output node. The voltage regulator has a charge pump circuit that receives a boosting control signal to boost the input voltage based on the boosting control signal. The voltage regulator further has a feedback regulation circuit configured to receive the output voltage and to provide a first operation control signal and a second operation control signal as a function of the output voltage; a phase control circuit configured to receive the first operation control signal and to provide the boosting control signal as a function of the first operation control signal; and a filter coupled to the output node, configured to receive the second operation control signal and configured to inject to or sink from the output node a charge that is a function of the second operation control signal.

First claim

What is claimed is:

1. A voltage regulator, comprising:
a charge pump circuit coupled between an input node of the voltage regulator and an output node of the voltage regulator, the charge pump circuit configured to generate an output voltage at the output node based on a respective boosting control signal, the output voltage having a boosted value with respect to an input voltage received at the input node;
a feedback regulation circuit configured to generate a first operation control signal and a second operation control signal as a function of the output voltage;
a phase control circuit configured to generate a boosting control signal as a function of the first operation control signal; and
a filter configured to inject into or sink from the output node, a charge that is a function of the second operation control signal.

2. The voltage regulator of claim 1 , wherein the filter comprises a capacitive element having a first terminal and a second terminal, the first terminal coupled to the output node, and the second terminal configured to receive the second operation control signal.

3. The voltage regulator of claim 1 , wherein the feedback regulation circuit comprises an inverter configured to receive the first operation control signal and generate the second operation control signal.

4. The voltage regulator of claim 3 , wherein the inverter is a first inverter, the feedback regulation circuit further comprising a second inverter configured to receive the second operation control signal and generate a third operation control signal, the filter comprising a capacitive element having a first terminal and a second terminal, the first terminal coupled to the output node, and the second terminal configured to receive the third operation control signal.

5. The voltage regulator of claim 4 , wherein the first inverter has a first response time in generating the second operation control signal in response to switching of the first operation control signal, and wherein the second inverter has a second response time in generating the third operation control signal in response to switching of the second operation control signal, the second response time being greater than the first response time.

6. The voltage regulator of claim 1 , wherein the feedback regulation circuit comprises a comparator configured to:
compare the output voltage to a reference voltage;
switch the first operation control signal to a first value in response to the output voltage being greater than the reference voltage; and
switch the first operation control signal to a second value in response to the output voltage being less than the reference voltage.

7. The voltage regulator of claim 6 , wherein the phase control circuit is configured to:
disable boosting of the input voltage by the charge pump circuit in response to the first operation control signal switching to the first value; and
enable the boosting of the input voltage by the charge pump circuit in response to the first operation control signal switching to the second value.

8. The voltage regulator of claim 1 , wherein the voltage regulator is a voltage regulator of a non-volatile memory.

9. The voltage regulator of claim 8 , wherein the non-volatile memory is a phase-change memory.

10. A method, comprising:
generating, by a charge pump circuit of a voltage regulator, an output voltage at an output node of the voltage regulator, the output voltage being a boosted value with respect to an input voltage received at an input node of the voltage regulator, the output voltage being based on a respective boosting control signal, the charge pump circuit coupled between the input node and the output node;
generating, by a feedback regulation circuit of the voltage regulator, a first operation control signal and a second operation control signal as a function of the output voltage;
generating, by a phase control circuit of the voltage regulator, a boosting control signal as a function of the first operation control signal; and
injecting into or sinking from, by a filter of the voltage regulator, the output node a charge that is a function of the second operation control signal.

11. The method of claim 10 , wherein generating the second operation control signal comprises inverting the first operation control signal to generate the second operation control signal.

12. The method of claim 10 , wherein the filter comprises a first capacitive element, a first terminal of the first capacitive element coupled to the output node, the method further comprising receiving the second operation control signal at a second terminal of the first capacitive element.

13. The method of claim 12 , wherein the filter comprises a second capacitive element, a first terminal of the second capacitive element coupled to the output node, the method further comprising:
generating, by the feedback regulation circuit, a third operation control signal; and
receiving, by a second terminal of the second capacitive element, the third operation control signal, the third operation control signal being an inverted signal with respect to the second operation control signal.

14. The method of claim 10 , further comprising:
comparing the output voltage to a reference voltage;
switching the first operation control signal to a first value in response to the output voltage being greater than the reference voltage; and
switching the first operation control signal to a second value in response to the output voltage being less than the reference voltage.

15. The method of claim 10 , wherein the step of injecting into or sinking from the output node is performed faster than a step of providing, by the phase control circuit, the respective boosting control signal to the charge pump circuit.

16. A device comprising a non-volatile memory having a voltage regulator, the voltage regulator comprising:
a charge pump circuit coupled between an input node of the voltage regulator and an output node of the voltage regulator, the charge pump circuit configured to generate an output voltage at the output node based on a respective boosting control signal, the output voltage having a boosted value with respect to an input voltage received at the input node;
a feedback regulation circuit configured to generate a first operation control signal and a second operation control signal as a function of the output voltage;
a phase control circuit configured to generate a boosting control signal as a function of the first operation control signal; and
a filter configured to inject into or sink from the output node, a charge that is a function of the second operation control signal.

17. The device of claim 16 , wherein the filter comprises a capacitive element having a first terminal and a second terminal, the first terminal coupled to the output node, and the second terminal configured to receive the second operation control signal, and wherein the feedback regulation circuit comprises an inverter configured to receive the first operation control signal and generate the second operation control signal.

18. The device of claim 17 , wherein the inverter is a first inverter, the feedback regulation circuit further comprising a second inverter configured to receive the second operation control signal and generate a third operation control signal, the filter comprising a capacitive element having a first terminal and a second terminal, the first terminal coupled to the output node, and the second terminal configured to receive the third operation control signal.

19. The de

Assignees

• St Microelectronics Srl

Inventors

• Capecchi Laura
• Carissimi Marcella
• Pasotti Marco
• Romele Paolo

Classifications

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M1/082

  with digital control · CPC title

• H02M1/0025

  Arrangements for modifying reference values, feedback values or error values in the control loop of a converter · CPC title

• H02M1/14

  Arrangements for reducing ripples from DC input or output · CPC title

• G05F1/56

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title