Integrated circuit including high-speed device

Patent metadata

Field	Value
Publication number	US-12451428-B2
Application number	US-202217837786-A
Country	US
Kind code	B2
Filing date	Jun 10, 2022
Priority date	Jun 10, 2021
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

An integrated circuit is provided. The integrated circuit includes: an active region extending in a first direction; gate electrodes extending in a second direction in parallel with each other; source/drain regions provided on the active region between the gate electrodes; a first gate contact connected to the gate electrodes and extending in the first direction; a first gate wiring pattern provided in a first wiring layer, electrically connected to the gate electrodes through the first gate contact, and overlapping the first gate contact along a third direction perpendicular to the first and second directions; and source/drain wiring patterns provided in a second wiring layer, electrically connected to the source/drain regions, respectively, extending in parallel with the second direction, and overlapping the source/drain regions along the third direction, the second wiring layer being provided on the first wiring layer.

First claim

What is claimed is:

1. An integrated circuit comprising:
an active region extending in a first direction;
a plurality of gate electrodes extending in a second direction in parallel with each other, the second direction being perpendicular to the first direction;
a plurality of source/drain regions provided on the active region between the plurality of gate electrodes;
a first gate contact connected to the plurality of gate electrodes and extending in the first direction;
a plurality of first gate wiring patterns provided in a first wiring layer, wherein each of the plurality of first gate wiring patterns are electrically connected to each of the plurality of gate electrodes through the first gate contact, wherein the plurality of first gate wiring patterns are spaced apart from each other along the first direction, wherein the plurality of first gate wiring patterns extend farther in the second direction than the first gate contact extends in the second direction, and wherein the first gate contact extends between the plurality of gate electrodes and the plurality of first gate wiring patterns along a third direction perpendicular to the first direction and the second direction; and
a plurality of source/drain wiring patterns provided in a second wiring layer, electrically connected to the plurality of source/drain regions, respectively, extending in parallel with the second direction, and overlapping the plurality of source/drain regions along the third direction, the second wiring layer being provided on the first wiring layer,
wherein the first gate contact overlaps at least one of the plurality of source/drain wiring patterns along the third direction.

2. The integrated circuit of claim 1 , further comprising:
a second gate contact connected to the plurality of gate electrodes and extending in the first direction; and
at least one second gate wiring pattern provided in the first wiring layer, electrically connected to the plurality of gate electrodes through the second gate contact, and wherein the second gate contact extends between the plurality of gate electrodes and the at least one second gate wiring pattern along the third direction,
wherein the second gate contact overlaps at least one of the plurality of source/drain wiring patterns along the third direction.

3. The integrated circuit of claim 2 , wherein the active region and a region between the first gate contact and the second gate contact overlap, along the third direction.

4. The integrated circuit of claim 3 , wherein the plurality of gate electrodes have a minimum length in the second direction between the active region and the first gate contact and between the active region and the second gate contact.

5. The integrated circuit of claim 2 , wherein the plurality of source/drain regions comprises:
a plurality of source regions electrically connected to each other; and
a plurality of drain regions electrically connected to each other, and
wherein the plurality of source/drain wiring patterns comprises:
source wiring patterns provided in the second wiring layer, and extending in the second direction from regions overlapping the plurality of source regions to regions overlapping the first gate contact, along the third direction; and
drain wiring patterns provided in the second wiring layer, and extending in an opposite direction to the second direction from regions overlapping the plurality of drain regions to regions overlapping the second gate contact, along the third direction.

6. The integrated circuit of claim 5 , wherein each of the source wiring patterns has an end which overlaps the active region along the third direction, and
wherein each of the drain wiring patterns has an end which overlaps the active region along the third direction.

7. The integrated circuit of claim 5 , further comprising:
a first pattern provided in a third wiring layer provided on the second wiring layer, electrically connected to the source wiring patterns, and extending in the first direction; and
a second pattern provided in the third wiring layer, electrically connected to the drain wiring patterns, and extending in the first direction.

8. The integrated circuit of claim 1 , wherein each of the plurality of first gate wiring patterns overlaps two of the plurality of gate electrodes along the third direction.

9. The integrated circuit of claim 1 , wherein the plurality of first gate wiring patterns comprises a pattern overlapping two of the plurality of gate electrodes along the third direction.

10. The integrated circuit of claim 1 , wherein a distance in the second direction between the first gate contact and the active region is a minimum space defined by a semiconductor process.

11. An integrated circuit comprising:
an active region extending in a first direction;
a plurality of gate electrodes extending in a second direction in parallel with each other, the second direction being perpendicular to the first direction;
a plurality of source regions each provided on the active region between gate electrodes and electrically connected to each other;
a plurality of drain regions each provided on the active region between gate electrodes and electrically connected to each other;
source wiring patterns electrically connected to the plurality of source regions, respectively, and extending in the second direction from regions which overlap the plurality of source regions, along a third direction perpendicular to the first direction and the second direction;
a first gate contact and a second gate contact, the first gate contact and the second gate contact being connected to the plurality of gate electrodes and extending in the first direction in parallel with each other,
a plurality of first gate wiring patterns electrically connected to each of the plurality of gate electrodes through the first gate contact, wherein the plurality of first gate wiring patterns are spaced apart from each other along the first direction, wherein the plurality of first gate wiring patterns extend farther in the second direction than the first gate contact extends in the second direction, and wherein the first gate contact extends between the plurality of gate electrodes and the plurality of first gate wiring patterns;
a plurality of second gate wiring patterns electrically connected to each of the plurality of gate electrodes through the second gate contact, wherein the plurality of second gate wiring patterns are spaced apart from each other along the first direction, and wherein the second gate contact extends between the plurality of gate electrodes and the plurality of second gate wiring patterns; and
drain wiring patterns electrically connected to the plurality of drain regions, respectively, and extending in an opposite direction to the second direction from regions which overlap the plurality of drain regions, along the third direction.

12. The integrated circuit of claim 11 , wherein each of the source wiring patterns and each of the drain wiring patterns comprises an end which overlaps the active region along the third direction.

13. The integrated circuit of claim 11 , wherein the active region and a region between the first gate contact and the second gate contact overlap, along the third direction,
wherein the source wiring patterns extend in the second direction to overlap the first gate contact along the third direction, and
wherein the drain wiring patterns extend in the opposite direction to the second direction to overlap the second gate contact along the third direction.

14. The integrated circuit of claim 13 , wherein the plurality of first gate wiring patt

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Gyeongseok
• Ko Kyeongjoon
• Park Jaehyun
• Bae Junhan
• Ryu Jongjae
• Lee Nakwon

Classifications

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D84/0149 Primary

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D89/10

  Integrated device layouts · CPC title