Memory system, memory and memory control method

Patent metadata

Field	Value
Publication number	US-12451193-B2
Application number	US-202318330120-A
Country	US
Kind code	B2
Filing date	Jun 6, 2023
Priority date	Dec 30, 2022
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

Devices, systems, and methods for counting a quantity of fail-bits in a memory device using a VFC circuit are disclosed. The VFC circuit can be calibrated via an offset adjustment mechanism to compensate an internal mismatch. The VFC circuit can include a processing unit and a circuit coupled to the processing unit. The processing unit can receive a first signal representing a number of detected fail-bits in the memory array, process the first signal and an offset signal, and generate a second signal representing a quantity of fail-bits. The circuit can receive the first and second signals, determine a difference between the quantity of fail-bits represented by the second signal and the number of detected fail-bits represented by the first signal, adjust the offset signal according to the difference, and provide the offset signal to the processing unit.

First claim

What is claimed is:

1. A memory device, comprising:
a memory array; and
a peripheral circuit, comprising:
a page buffer coupled to the memory array and configured to detect fail-bits in the memory array;
a verify fail-bit count (VFC) circuit coupled to the page buffer, wherein the VFC circuit includes a comparator unit configured to determine a mismatch and a trimming unit configured to generate an offset signal to compensate the mismatch in the VFC circuit such that the VFC circuit outputs a quantity of the fail-bits in the memory array, wherein the trimming unit is further configured to:
decrease the offset signal, if the mismatch is positive; and
increase the offset signal, if the mismatch is negative; and

a control circuit coupled to the VFC circuit and configured to control an adjustment of the offset signal.

2. The memory device of claim 1 , wherein the VFC circuit is further configured to adjust the offset signal according to the mismatch.

3. The memory device of claim 1 , wherein the VFC circuit further comprises a processing unit coupled to the trimming unit and the comparator unit and configured to output the quantity of the fail-bits by combining the offset signal and an input signal representing the detected fail-bits.

4. The memory device of claim 3 , wherein:
the control circuit is further configured to provide a calibration signal; and
the comparator unit is further configured to determine the mismatch by comparing the calibration signal and an output signal of the processing unit.

5. The memory device of claim 1 , wherein the offset signal is decreased or increased by a constant value corresponding to changing the quantity of the fail-bits by 1.

6. A memory system, comprising:
a memory controller; and
one or more memory devices controlled by the memory controller, wherein each of the one or more memory devices comprises:
a memory array; and
a peripheral circuit, comprising:
a page buffer coupled to the memory array and configured to detect fail-bits in the memory array;
a verify fail-bit count (VFC) circuit coupled to the page buffer, wherein the VFC circuit includes a comparator unit configured to determine a mismatch and a trimming unit configured to generate an offset signal to compensate the mismatch in the VFC circuit such that the VFC circuit outputs a quantity of the fail-bits in the memory array, wherein the trimming unit is further configured to:
decrease the offset signal, if the mismatch is positive; and
increase the offset signal, if the mismatch is negative; and

a control circuit coupled to the VFC circuit and configured to control an adjustment of the offset signal.

7. The memory system of claim 6 , wherein the VFC circuit is further configured to adjust the offset signal according to the mismatch.

8. The memory system of claim 7 , wherein the offset signal is decreased or increased by a constant value corresponding to changing the quantity of the fail-bits by 1.

9. The memory system of claim 6 , wherein the VFC circuit further comprises a processing unit coupled to the trimming unit and the comparator unit and configured to output the quantity of the fail-bits by combining the offset signal and an input signal representing the detected fail-bits.

10. The memory system of claim 9 , wherein:
the control circuit is further configured to provide a calibration signal; and
the comparator unit is further configured to determine the mismatch by comparing the calibration signal and an output signal of the processing unit.

11. A method, comprising:
detecting fail-bits in a memory array of a memory device by a page buffer coupled to the memory array;
generating an offset signal, by a verify fail-bit count (VFC) circuit coupled to the page buffer, to compensate a mismatch in the VFC circuit;
adjusting, under a control of a control circuit coupled to the VFC circuit, the offset signal according to the mismatch, wherein adjusting the offset signal further includes:
increasing the offset signal by a constant value, if the mismatch is negative; and
decreasing the offset signal by the constant value, if the mismatch is positive; and

providing, by the VFC circuit, a quantity of the fail-bits of the memory array.

12. The method of claim 11 , further comprising determining the mismatch by a comparator unit of the VFC circuit.

13. The method of claim 11 , wherein generating the offset signal comprises providing the offset signal by a trimming unit of the VFC circuit.

14. The method of claim 11 , further comprising receiving, by the VFC circuit, an input signal comprising a plurality of current signals, each representing a detection of a fail-bit.

15. The method of claim 11 , wherein providing the quantity of the fail-bits comprises providing a voltage signal having an amplitude proportional to the quantity of the fail-bits.

16. The method of claim 11 , further comprising comparing the quantity of fail-bits and a baseline quantity corresponding to a quality standard.

17. The method of claim 11 , further comprising outputting, under a control of a trimming unit and a comparator unit of a VFC circuit, the quantity of the fail-bits, the quantity of fail-bits calculated by combining the offset signal and an input signal representing the detected fail-bits.

18. The method of claim 17 , further comprising providing a calibration signal.

19. The method of claim 18 , further comprising determining the mismatch by comparing the calibration signal and an output signal of a processing unit, the processing unit coupled to the trimming unit and the comparator unit of the VFC circuit.

20. The method of claim 11 , further comprising decreasing or increasing by the constant value the offset signal by the constant value corresponding to changing the quantity of the fail-bits by 1.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Cao Yi
• Liang Ke
• Qiao Liang

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C2029/0409

  Online test · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title