Display driver system with embedded non-volatile memory

Patent metadata

Field	Value
Publication number	US-12451101-B2
Application number	US-202318374541-A
Country	US
Kind code	B2
Filing date	Sep 28, 2023
Priority date	Apr 10, 2019
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

Circuitry for adjusting luminance of a display device is provided. The circuitry includes a non-volatile memory array having a plurality memory cells configured to store luminance data of the display device, and a luminance adjusting circuit configured to receive image data to be displayed on the display device. The luminance adjusting circuit is coupled directly to the non-volatile memory array to receive the luminance data of the display device from the non-volatile memory array and adjust the image data based on the luminance data of the display device.

First claim

What is claimed is:

1. An apparatus comprising:
circuitry for adjusting luminance of a display device, comprising:
a non-volatile memory array having a plurality of memory cells configured to store luminance data of the display device, and
a luminance adjusting circuit configured to receive image data to be displayed on the display device and adjust the image data based on the luminance data of the display device; and

a unified controller configured to provide (i) memory control signals to control operations of the non-volatile memory array and (ii) luminance control signals to control operations of the luminance adjusting circuit.

2. The apparatus of claim 1 , wherein the unified controller comprises:
a single finite state machine configured to generate (i) the memory control signals and (ii) the luminance control signals.

3. The apparatus of claim 1 , wherein:
the circuitry for adjusting luminance of a display device further comprises a further non-volatile memory array having a further plurality of memory cells configured to buffer the image data prior to the luminance adjusting circuit adjusting the image data; and
the unified controller is further configured provide (iii) further memory control signals to control operations of the further non-volatile memory array.

4. The apparatus of claim 3 , wherein the unified controller comprises:
a single finite state machine configured to generate (i) the memory control signals, (ii) the luminance control signals, and (iii) the further memory control signals.

5. A single integrated circuit comprising the apparatus of claim 1 .

6. The apparatus of claim 1 , wherein the non-volatile memory array includes one of a resistive random access memory, a phase-change random access memory, a ferroelectric random access memory, or a spin-transfer torque magnetic random access memory.

7. The apparatus of claim 1 , wherein the non-volatile memory array is a one-time programmable memory.

8. The apparatus of claim 7 , wherein the non-volatile memory array includes a redundant memory section configured to correct an error of the luminance data after the one-time programmable memory is programmed with the luminance data.

9. The apparatus of claim 1 , wherein the non-volatile memory array includes a plurality of memory banks, and wherein the luminance adjusting circuit is configured to receive in parallel a set of data from the plurality of memory banks and output in series pixel data corresponding to the set of data.

10. The apparatus of claim 1 , wherein the unified controller comprises:
a non-volatile memory, the unified controller configured to provide the memory control signals and the luminance control signals in accordance with data stored in the non-volatile memory.

11. An apparatus comprising:
circuitry for adjusting luminance of a display device, comprising:
a non-volatile memory array having a plurality of memory cells configured to store luminance data of the display device, and
a luminance adjusting circuit configured to receive image data to be displayed on the display device and adjust the image data based on the luminance data of the display device;

a luminance controller comprising a first non-volatile memory, the luminance controller configured to provide luminance control signals to control operations of the luminance adjusting circuit in accordance with first data stored in the first non-volatile memory; and
a memory controller comprising a second non-volatile memory, the memory controller configured to provide memory control signals to control operations of the non-volatile memory array in accordance with second data stored in the second non-volatile memory.

12. The apparatus of claim 11 , wherein the luminance controller comprises:
a single finite state machine configured to generate the luminance control signals.

13. The apparatus of claim 11 , wherein the memory controller comprises:
a single finite state machine configured to generate the memory control signals.

14. The apparatus of claim 11 , wherein:
the circuitry for adjusting luminance of a display device further comprises a further non-volatile memory array having a further plurality of memory cells configured to buffer the image data prior to the luminance adjusting circuit adjusting the image data; and
the memory controller is further configured provide further memory control signals to control operations of the further non-volatile memory array.

15. The apparatus of claim 14 , wherein the memory controller comprises:
a single finite state machine configured to generate the memory control signals and the further memory control signals.

16. A single integrated circuit comprising the apparatus of claim 11 .

17. The apparatus of claim 11 , wherein the non-volatile memory array includes one of a resistive random access memory, a phase-change random access memory, a ferroelectric random access memory, or a spin-transfer torque magnetic random access memory.

18. The apparatus of claim 11 , wherein the non-volatile memory array is a one-time programmable memory.

19. The apparatus of claim 18 , wherein the non-volatile memory array includes a redundant memory section configured to correct an error of the luminance data after the one-time programmable memory is programmed with the luminance data.

20. The apparatus of claim 11 , wherein the non-volatile memory array includes a plurality of memory banks, and wherein the luminance adjusting circuit is configured to receive in parallel a set of data from the plurality of memory banks and output in series pixel data corresponding to the set of data.

Assignees

• Hefei Reliance Memory Ltd

Inventors

• Zhao Liang
• Lu Zhichao
• Han Zhigang

Classifications

• H04N5/57

  Control of contrast or brightness · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G3/2007

  Display of intermediate tones · CPC title

• G09G2360/128

  Frame memory using a Synchronous Dynamic RAM [SDRAM] · CPC title