Shift register, scanning driving circuit and displaying device

Patent metadata

Field	Value
Publication number	US-12451081-B2
Application number	US-202318576574-A
Country	US
Kind code	B2
Filing date	Apr 28, 2023
Priority date	Apr 28, 2023
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

The present application relates to a shift register, a scanning driving circuit and a displaying device. The shift register includes a first inputting circuit, a first outputting circuit, a second inputting circuit, a second outputting circuit and a second controlling circuit. The second controlling circuit is electrically connected to a first node, a second node, a fifth voltage terminal, a second clock-signal terminal and a controlling terminal. The second controlling circuit is configured for, under the control of the signal of the second node, the control of a second clock signal and the control of the signal of the controlling terminal, when the first outputting circuit is switched on, disconnecting the electric connection between the first node and the fifth voltage terminal, and when the second outputting circuit is switched on, writing the signal of the fifth voltage terminal into the first node.

First claim

The invention claimed is:

1. A shift register, wherein the shift register comprises:
a first inputting circuit electrically connected to a start-signal terminal, a first node and a first clock-signal terminal, wherein the first inputting circuit is configured for, under control of a first clock signal of the first clock-signal terminal, writing a signal of the start-signal terminal into the first node;
a first outputting circuit electrically connected to the first node, an output terminal and a first voltage terminal, wherein the first outputting circuit is configured for, when switched on under control of a signal of the first node, writing a signal of the first voltage terminal into the output terminal;
a second inputting circuit electrically connected to the first node, a second node, a second voltage terminal and the first clock-signal terminal, wherein the second inputting circuit is configured for, under the control of the signal of the first node, writing the first clock signal into the second node, and, under the control of the first clock signal, writing a signal of the second voltage terminal into the second node;
a second outputting circuit electrically connected to a fourth voltage terminal, the second node and the output terminal, wherein the second outputting circuit is configured for, when switched on under control of a signal of the second node, writing a signal of the fourth voltage terminal into the output terminal; and
a second controlling circuit electrically connected to the first node, the second node, a fifth voltage terminal, a second clock-signal terminal and a controlling terminal, wherein the second controlling circuit is configured for, under the control of the signal of the second node, control of a second clock signal and control of a signal of the controlling terminal, when the first outputting circuit is switched on, disconnecting electric connection between the first node and the fifth voltage terminal, and when the second outputting circuit is switched on, writing a signal of the fifth voltage terminal into the first node,
wherein the second controlling circuit comprises a first sub-circuit and a second sub-circuit that are connected in series between the fifth voltage terminal and the first node,
the second sub-circuit is electrically connected to the controlling terminal, and the second sub-circuit is configured for, under the control of the signal of the controlling terminal, being disconnected when the first outputting circuit is switched on, and being switched on when the second outputting circuit is switched on,
the first sub-circuit is electrically connected to the second node and the second clock-signal terminal, and the first sub-circuit is configured for, when switched on under the control of the signal of the second node and the control of the second clock signal of the second clock-signal terminal, cooperating with the second sub-circuit to write the signal of the fifth voltage terminal into the first node, and
the controlling terminal is electrically connected to a fourth node.

2. The shift register according to claim 1 , wherein the shift register further comprises a first controlling circuit, the first controlling circuit is electrically connected to the first node, the second node, a fourth node, the second clock-signal terminal and a third voltage terminal, and the first controlling circuit is configured for, under the control of the signal of the second node and the control of the second clock signal of the second clock-signal terminal, writing the second clock signal into the fourth node, and, under the control of the signal of the first node, writing a signal of the third voltage terminal into the fourth node.

3. The shift register according to claim 2 , wherein the controlling terminal is electrically connected to the fourth node.

4. The shift register according to claim 2 , wherein the first inputting circuit comprises a first transistor, a first electrode of the first transistor is electrically connected to the start-signal terminal, a second electrode of the first transistor is electrically connected to the first node, and a control electrode of the first transistor is electrically connected to the first clock-signal terminal.

5. The shift register according to claim 1 , wherein the first sub-circuit comprises a fourth transistor and a fifth transistor, a control electrode of the fourth transistor is electrically connected to the second clock-signal terminal, and a first electrode of the fourth transistor is electrically connected to the first node; a control electrode of the fifth transistor is electrically connected to the second node, a first electrode of the fifth transistor is electrically connected to a second electrode of the fourth transistor, and a second electrode of the fifth transistor is electrically connected to the fifth voltage terminal, and
the second sub-circuit is electrically connected between the fourth transistor and the fifth transistor, or between the fourth transistor and the first node, or between the fifth transistor and the fifth voltage terminal.

6. The shift register according to claim 5 , wherein the second sub-circuit comprises an eleventh transistor, and a control electrode of the eleventh transistor is electrically connected to the controlling terminal; and
a first electrode of the eleventh transistor is electrically connected to the first node, and a second electrode of the eleventh transistor is electrically connected to the first electrode of the fourth transistor; or
the first electrode of the eleventh transistor is electrically connected to the second electrode of the fourth transistor, and the second electrode of the eleventh transistor is electrically connected to the first electrode of the fifth transistor; or
the first electrode of the eleventh transistor is electrically connected to the second electrode of the fifth transistor, and the second electrode of the eleventh transistor is electrically connected to the fifth voltage terminal.

7. The shift register according to claim 1 , wherein the first inputting circuit comprises a first transistor, a first electrode of the first transistor is electrically connected to the start-signal terminal, a second electrode of the first transistor is electrically connected to the first node, and a control electrode of the first transistor is electrically connected to the first clock-signal terminal.

8. The shift register according to claim 1 , wherein the first outputting circuit comprises a tenth transistor, a first electrode of the tenth transistor is electrically connected to the output terminal, a second electrode of the tenth transistor is electrically connected to the first voltage terminal, and a control electrode of the tenth transistor is electrically connected to the first node.

9. The shift register according to claim 8 , wherein the first outputting circuit further comprises a first capacitor, one of polar plates of the first capacitor is electrically connected to the first node, and the other of the polar plates of the first capacitor is electrically connected to the output terminal.

10. The shift register according to claim 1 , wherein the second inputting circuit comprises:
a second transistor, wherein a control electrode of the second transistor is electrically connected to the first node, a first electrode of the second transistor is electrically connected to the second node, and a second electrode of the second transistor is electrically connected to the first clock-signal terminal; and
a third transistor, wherein a control electrode of the third transistor is electrically connected to the first clock-signal terminal, a first electrode of the third transistor is ele

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Zhang Jingwen
• Huang Yao
• Wang Binyan

Classifications

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• H10K59/12

  Active-matrix OLED [AMOLED] displays · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title