Pixel circuit and driving method therefor, display panel, and display device

Patent metadata

Field	Value
Publication number	US-12451076-B2
Application number	US-202418938338-A
Country	US
Kind code	B2
Filing date	Nov 6, 2024
Priority date	Jul 21, 2022
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

A pixel circuit includes a driving circuit, a control circuit and a gating circuit. The driving circuit is configured to control, under control of a scan signal and a signal received at an enable signal control terminal, on and off of a current path for transmitting a driving current signal. The control circuit is configured to transmit, under control of a control signal received at a control signal terminal, a first enable signal received at a first enable signal terminal or a second enable signal received at a second enable signal terminal to a first node. The gating circuit is configured to transmit, in response to an enable signal received at the first node, a first constant voltage signal received at the first constant voltage signal terminal or a second constant voltage signal received at the second constant voltage signal terminal to the enable signal control terminal.

First claim

What is claimed is:

1. A pixel circuit, comprising:
a driving circuit coupled to a grayscale data signal terminal, a scan signal terminal, a first power supply voltage terminal, an enable signal control terminal and a light-emitting device; the driving circuit being configured to control on and off of a current path for transmitting a driving current signal under control of a scan signal received at the scan signal terminal and a signal received at the enable signal control terminal;
a control circuit coupled to a control signal terminal, a first node, a first enable signal terminal and a second enable signal terminal; the control circuit being configured to transmit a first enable signal received at the first enable signal terminal or a second enable signal received at the second enable signal terminal to the first node under control of a control signal received at the control signal terminal; and
a gating circuit coupled to the enable signal control terminal, the first node, a first constant voltage signal terminal and a second constant voltage signal terminal; the gating circuit being configured to, in response to an enable signal received at the first node, transmit a first constant voltage signal received at the first constant voltage signal terminal or a second constant voltage signal received at the second constant voltage signal terminal to the enable signal control terminal.

2. The pixel circuit according to claim 1 , wherein the gating circuit includes:
a first output sub-circuit coupled to the enable signal control terminal, the first node and the first constant voltage signal terminal; the first output sub-circuit being configured to, in response to the enable signal received at the first node, transmit the first constant voltage signal received at the first constant voltage signal terminal to the enable signal control terminal; and
a second output sub-circuit coupled to the enable signal control terminal, the first node and the second constant voltage signal terminal; the second output sub-circuit being configured to, in response to the enable signal received at the first node, transmit the second constant voltage signal received at the second constant voltage signal terminal to the enable signal control terminal.

3. The pixel circuit according to claim 2 , wherein
the first output sub-circuit includes: a first transistor, wherein a first electrode of the first transistor is coupled to the first constant voltage signal terminal, a second electrode of the first transistor is coupled to the enable signal control terminal, and a control electrode of the first transistor is coupled to the first node; and
the second output sub-circuit includes: a second transistor having an inverse conduction type to the first transistor, wherein a first electrode of the second transistor is coupled to the second constant voltage signal terminal, a second electrode of the second transistor is coupled to the enable signal control terminal, and a control electrode of the second transistor is coupled to the first node;
or
the first output sub-circuit includes: a first transistor, wherein a first electrode of the first transistor is coupled to the first constant voltage signal terminal, a second electrode of the first transistor is coupled to the enable signal control terminal, and a control electrode of the first transistor is coupled to the first node; and
the second output sub-circuit includes: a second transistor having an inverse conduction type to the first transistor, wherein a first electrode of the second transistor is coupled to the second constant voltage signal terminal, a second electrode of the second transistor is coupled to the enable signal control terminal, and a control electrode of the second transistor is coupled to the first node; wherein
the first constant voltage signal received at the first constant voltage signal terminal is greater than the second constant voltage signal received at the second constant voltage signal terminal; the first transistor is a P-type transistor, and the second transistor is an N-type transistor.

4. The pixel circuit according to claim 1 , wherein the driving circuit includes:
a data writing sub-circuit coupled to the grayscale data signal terminal, the scan signal terminal and a second node; the data writing sub-circuit being configured to transmit a grayscale data signal received at the grayscale data signal terminal to the second node in response to the scan signal received at the scan signal terminal; and
a driving signal generation sub-circuit coupled to the second node, the first power supply voltage terminal, the enable signal control terminal and the light-emitting device; the driving signal generation sub-circuit being configured to generate the driving current signal based on a voltage at the second node and a first voltage signal received at the first power supply voltage terminal, and control the on and off of the current path for transmitting the driving current signal in response to the signal received at the enable signal control terminal.

5. The pixel circuit according to claim 4 , wherein the driving signal generation sub-circuit includes:
a third transistor, wherein a first electrode of the third transistor is coupled to a third node, a second electrode of the third transistor is coupled to a fourth node, and a control electrode of the third transistor is coupled to the second node; the fourth node is further coupled to a first electrode of the light-emitting device, and a second electrode of the light-emitting device is coupled to a second power supply voltage terminal; and
a fourth transistor, wherein a first electrode of the fourth transistor is coupled to the first power supply voltage terminal, a second electrode of the fourth transistor is coupled to the third node, and a control electrode of the fourth transistor is coupled to the enable signal control terminal.

6. The pixel circuit according to claim 4 , wherein the data writing sub-circuit is further coupled to a reference voltage terminal, and the scan signal terminal includes a first scan signal terminal and a second scan signal terminal;
the data writing sub-circuit includes:
a fifth transistor, wherein a first electrode of the fifth transistor is coupled to the grayscale data signal terminal, a second electrode of the fifth transistor is coupled to the second node, and a control electrode of the fifth transistor is coupled to the first scan signal terminal;
a sixth transistor having an inverse conduction type to the fifth transistor, wherein a first electrode of the sixth transistor is coupled to the grayscale data signal terminal, a second electrode of the sixth transistor is coupled to the second node, and a control electrode of the sixth transistor is coupled to the second scan signal terminal; and
a first capacitor, wherein a first electrode plate of the first capacitor is coupled to the second node, and a second electrode plate of the first capacitor is coupled to a reference voltage terminal.

7. The pixel circuit according to claim 4 , wherein the driving circuit further includes:
a reset sub-circuit coupled to the scan signal terminal, a fourth node and a reset signal terminal; the reset sub-circuit being configured to, in response to the scan signal received at the scan signal terminal, transmit a reset signal received at the reset signal terminal to the fourth node; or
the driving circuit further includes:
a reset sub-circuit coupled to the scan signal terminal, a fourth node and a reset signal terminal; the reset sub-circuit being configured to, in response to the scan signal received at the scan signal terminal, transmit a reset signal received at the reset signal terminal to the fourth node; and the reset sub-circuit including a sev

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Cong Ning
• Zhang Can
• Xuan Minghua
• Niu Jinfei
• Wang Can
• Zhang Jingjing
• Yan Jiakui

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/062

  Waveforms for resetting a plurality of scan lines at a time · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/027

  Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters · CPC title

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title