Pixel circuit and display device

Patent metadata

Field	Value
Publication number	US-12451050-B2
Application number	US-202218262893-A
Country	US
Kind code	B2
Filing date	Jul 29, 2022
Priority date	Jul 29, 2022
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

A pixel circuit includes a light emitting circuit, a light emitting control circuit, a first control circuit and a switch control circuit; the light emitting control circuit controls to connect the control voltage input terminal and the light emitting circuit under the control of a light emitting control signal provided by the light emitting control terminal; the light emitting circuit emits light according to a control voltage provided by the control voltage input terminal; the first control circuit controls a switch control signal under the control of a scanning signal according to a data voltage; N is an integer greater than 1; the switch control circuit includes N switch control terminals, N light emitting control voltage terminals and N switch control sub-circuits; n is a positive integer less than or equal to N.

First claim

What is claimed is:

1. A pixel circuit, comprising a light emitting circuit, a light emitting control circuit, a first control circuit and a switch control circuit; wherein
the light emitting control circuit is electrically connected to a light emitting control terminal, a control voltage input terminal and the light emitting circuit respectively, and is configured to control to connect the control voltage input terminal and the light emitting circuit under the control of a light emitting control signal provided by the light emitting control terminal;
the light emitting circuit is configured to emit light according to a control voltage provided by the control voltage input terminal;
the first control circuit is electrically connected to at least two data voltage terminals, at least two scanning terminals, and N switch control terminals, and is configured to control a switch control signal provided to the switch control terminal under the control of a scanning signal provided by the scanning terminal according to a data voltage provided by the data voltage terminal; N is an integer greater than 1;
the switch control circuit includes N switch control terminals, N light emitting control voltage terminals and N switch control sub-circuits; n is a positive integer less than or equal to N;
an nth switch control sub-circuit is electrically connected to an nth switch control terminal, an nth light emitting control voltage terminal and the control voltage input terminal respectively, and is configured to control to connect the nth light emitting control voltage terminal and the control voltage input terminal under the control of an nth switch control signal provided by the nth switch control terminal.

2. The pixel circuit according to claim 1 , wherein a light emitting control voltage provided by the light emitting control voltage terminal is a direct current voltage, and the light emitting control voltages provided by the N light emitting control voltage terminals are different from each other.

3. The pixel circuit according to claim 1 , wherein a light emitting control voltage provided by the light emitting control voltage terminal is a square wave voltage signal, and duty ratios of light emitting control voltages provided by the N light emitting control voltage terminals are different from each other.

4. The pixel circuit according to claim 1 , wherein N is equal to 2ª, and a is a positive integer.

5. The pixel circuit according to claim 1 , wherein the first control circuit includes a first data writing-in circuit, a second data writing-in circuit and a first control sub-circuit;
the first data writing-in circuit is electrically connected to a first scanning terminal, a first data voltage terminal and a first data access terminal respectively, and is configured to write a first data voltage provided by the first data voltage terminal into the first data access terminal under the control of a first scanning signal provided by the first scanning terminal;
the second data writing-in circuit is electrically connected to a second scanning terminal, a second data voltage terminal and a second data access terminal respectively, and is configured to write a second data voltage provided by the second data voltage terminal into a second data access terminal under the control of a second scanning signal provided by the second scanning terminal;
the first control sub-circuit is electrically connected to the first data access terminal, the second data access terminal and the N switch control terminals respectively, and is configured to control to provide corresponding switch control signals to the N switch control terminals respectively according to a potential of the first data access terminal and a potential of the second data access terminal.

6. The pixel circuit according to claim 5 , wherein the first control sub-circuit includes a first latch, a second latch, a third latch, a fourth latch, a first control switch, and a second control switch; N is equal to 4;
an input terminal of the first latch is electrically connected to the first data access terminal, an output terminal of the first latch is electrically connected to a control terminal of the first control switch, and the first latch is configured to latch a voltage signal connected to the first data access terminal, and output a first output voltage, and the first output voltage is inverse in phase to the voltage signal connected to the first data access terminal;
an input terminal of the second latch is electrically connected to the second data access terminal, an output terminal of the second latch is electrically connected to a control terminal of the second control switch, and the second latch is configured to latch a voltage signal connected to the second data access terminal, and output a second output voltage, and the second output voltage is inverse in phase to the voltage signal connected to the second data access terminal;
an input terminal of the third latch is electrically connected to a first terminal of the first control switch, an output terminal of the third latch is electrically connected to the first switch control terminal, and the third latch is configured to latch a voltage signal connected to the input terminal of the third latch, and output a third output voltage, the third output voltage is inverse in phase the voltage signal connected to the input terminal of the third latch;
an input terminal of the fourth latch is electrically connected to a first terminal of the second control switch, an output terminal of the fourth latch is electrically connected to a third switch control terminal, and the fourth latch is configured to latch a voltage signal connected to an input terminal of the fourth latch, and output a fourth output voltage, the fourth output voltage is inverse in phase to the voltage signal connected to the input terminal of the fourth latch;
a control terminal of the first control switch is electrically connected to the output terminal of the first latch, a second terminal of the first control switch is electrically connected to the output terminal of the second latch, and the first control switch is configured to control to connect or disconnect the first terminal of the first control switch and the second terminal of the first control switch under the control of a potential of the control terminal of the first control switch;
a control terminal of the second control switch is electrically connected to the input terminal of the first latch, a second terminal of the second control switch is electrically connected to the input terminal of the second latch, and the second control switch is configured to control to connect or disconnect the first terminal of the second control switch and the second terminal of the second control switch under the control of a potential of the control terminal of the second control switch;
the first switch control terminal is electrically connected to the output terminal of the third latch, and the second switch control terminal is electrically connected to the input terminal of the third latch;
the third switch control terminal is electrically connected to the output terminal of the fourth latch, and the fourth switch control terminal is electrically connected to the input terminal of the fourth latch.

7. The pixel circuit according to claim 6 , wherein the first latch includes a first inverter and a second inverter;
an input terminal of the first inverter is electrically connected to the input terminal of the first latch, and an output terminal of the first inverter is electrically connected to the output terminal of the first latch;
an input terminal of the second inverter is electrically connected to the output terminal of the first inverter, and an output terminal

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Cong Ning
• Xuan Minghua
• Zhang Can
• Wang Can
• Niu Jinfei
• Zhang Jingjing

Classifications

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title