Driver module and display device

Patent metadata

Field	Value
Publication number	US-12451046-B2
Application number	US-202318577661-A
Country	US
Kind code	B2
Filing date	Feb 22, 2023
Priority date	Feb 22, 2023
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

A driver module includes a first driver unit and a first control unit; the first driver unit includes M levels of first driver circuits; M is a positive integer; m is a positive integer less than or equal to M; the m-th level first drive signal output terminal is electrically connected to a first terminal of an m-th row first gate line, to provide an m-th level first drive signal to the m-th row first gate line; the first control unit includes M first control circuits; an m-th first control circuit included in the first control unit is electrically connected to a second terminal of the m-th row first gate line, configured to control the second terminal of the m-th row first gate line to receive an ineffective voltage signal when a voltage value of the m-th level first drive signal changes from an effective voltage to an ineffective voltage.

First claim

What is claimed is:

1. A driver module, applied to a display device including M rows of first gate lines; the driver module comprising: a first driver unit and a first control unit; wherein the first driver unit comprises M levels of first driver circuits; an m-th level first driver circuit comprises an m-th level first drive signal output terminal; M is a positive integer; m is a positive integer less than or equal to M;
the m-th level first drive signal output terminal is electrically connected to a first terminal of an m-th row first gate line, and is configured to provide an m-th level first drive signal to the m-th row first gate line through the m-th level first drive signal output terminal;
the first control unit comprises M first control circuits;
an m-th first control circuit comprised in the first control unit is electrically connected to a second terminal of the m-th row first gate line, and configured to control the second terminal of the m-th row first gate line to receive an ineffective voltage signal when a voltage value of the m-th level first drive signal changes from an effective voltage to an ineffective voltage;
the first terminal and the second terminal are opposite terminals;
wherein the m-th first control circuit is configured to control a connection between the second terminal of the m-th row first gate line and a first voltage signal terminal, under control of an m-th first control signal provided by an m-th first control terminal;
wherein the m-th level first driver circuit is electrically connected to an m-th level first output clock signal line, and configured to, under control of a potential of an m-th level first pull-up node, control the m-th level first output clock signal line to provide an m-th level first output clock signal to the m-th level first drive signal output terminal;
the m-th first control terminal is electrically connected to an m-th first control clock signal line;
the m-th first control clock signal line is configured to provide an m-th first control clock signal;
the m-th level first output clock signal and the m-th first control clock signal are reciprocal signals.

2. The driver module according to claim 1 , wherein the display device further comprises N rows of second gate lines; the driver module further comprises a second driver unit and a second control unit; the second driver unit comprises N levels of second driver circuits; an n-th level second driver circuit comprises an n-th level second drive signal output terminal; N is a positive integer; n is a positive integer less than or equal to N;
the n-th level second drive signal output terminal is electrically connected to a second terminal of an n-th row second gate line, and configured to provide an n-th level second drive signal to the n-th row second gate line through the n-th level second drive signal output terminal;
the second control unit comprises N second control circuits;
an n-th second control circuit comprised in the second control unit is electrically connected to a first terminal of the n-th row second gate line, and configured to control the first terminal of the n-th row second gate line to receive an ineffective voltage signal when a voltage value of the n-th level second drive signal changes from an effective voltage to an ineffective voltage.

3. The driver module according to claim 2 , wherein the n-th second control circuit is configured to, under control of an n-th second control signal provided by an n-th second control terminal, control a connection between the first terminal of the n-th row second gate line and a second voltage signal terminal.

4. The driver module according to claim 3 , wherein the n-th second control circuit comprises an n-th second control transistor;
a gate of the n-th second control transistor is electrically connected to the n-th second control terminal, a first pole of the n-th second control transistor is electrically connected to the first terminal of the n-th row second gate line, and a second pole of the n-th second control transistor is electrically connected to the second voltage signal terminal;
or,
wherein the n-th level second driver circuit is electrically connected to an n-th level second output clock signal line, and configured to, under control of a potential of an n-th level second pull-up node, control the n-th level second output clock signal line to provide an n-th level second output clock signal to the n-th level second drive signal output terminal;
the n-th second control terminal is electrically connected to an n-th second control clock signal line;
the n-th second control clock signal line is configured to provide an n-th second control clock signal;
the n-th level second output clock signal and the n-th second control clock signal are reciprocal signals.

5. The driver module according to claim 4 , wherein the n-th level second driver circuit comprises an n-th level second driver transistor;
a gate of the n-th level second driver transistor is electrically connected to the n-th level second pull-up node, a first pole of the n-th level second driver transistor is electrically connected to the n-th level second output clock signal line, and a second pole of the n-th level second driver transistor is electrically connected to the n-th level second drive signal output terminal;
a channel width of the n-th second control transistor is greater than or equal to a third width but less than or equal to a fourth width;
a channel length of the n-th second control transistor is greater than a channel length of the n-th level second driver transistor;
the third width is half of a channel width of the n-th level second driver transistor;
the fourth width is 1.5 times the channel width of the n-th level second driver transistor.

6. The driver module according to claim 3 , wherein the second voltage signal terminal is a direct current voltage signal terminal, and the second voltage signal terminal is configured to provide an ineffective voltage signal; or,
wherein the second voltage signal terminal is electrically connected to the n-th level second output clock signal line.

7. The driver module according to claim 1 , wherein, the m-th first control circuit comprises an m-th first control transistor;
a gate of the m-th first control transistor is electrically connected to the m-th first control terminal, a first pole of the m-th first control transistor is electrically connected to the second terminal of the m-th row first gate line, and a second pole of the m-th first control transistor is electrically connected to the first voltage signal terminal.

8. The driver module according to claim 7 , wherein the m-th level first driver circuit comprises an m-th level first driver transistor;
a gate of the m-th level first driver transistor is electrically connected to the m-th level first pull-up node, a first pole of the m-th level first driver transistor is electrically connected to the m-th level first output clock signal line, and a second pole of the m-th level first driver transistor is electrically connected to the m-th level first drive signal output terminal;
a channel width of the m-th first control transistor is greater than or equal to a first width but less than or equal to a second width;
a channel length of the m-th first control transistor is greater than a channel length of the m-th level first driver transistor;
the first width is half of a channel width of the m-th level first driver transistor;
the second width is 1.5 times the channel width of the m-th level first driver transistor.

9. The driver module according to claim 1 , wherein the first voltage signal terminal is a direct current voltage signal terminal, and the first voltage

Assignees

• Fuzhou Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Fang Xin
• Wang Wenchao
• Park Sangjin
• Chen Jixiang
• Chen Xiaolong
• Zhang Lixia

Classifications

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/2092 Primary

  Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165) · CPC title