Apparatus and method for routing data from ray tracing cache banks

Patent metadata

Field	Value
Publication number	US-12450819-B2
Application number	US-202217826090-A
Country	US
Kind code	B2
Filing date	May 26, 2022
Priority date	May 26, 2022
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

For example, one embodiment of an apparatus comprises: ray traversal hardware logic to perform traversal operations to traverse rays through a bounding volume hierarchy (BVH) comprising a plurality of BVH nodes, the ray traversal hardware logic comprising a plurality of traversal storage banks to store traversal data associated with the BVH nodes and/or the rays as the ray traversal hardware logic performs the traversal operations; and a cache comprising a plurality of cache banks to store the traversal data prior to being moved into the traversal storage banks for processing by the ray traversal hardware logic; and an inter-bank interconnect comprising: a point-to-point switch matrix to couple any of the cache banks to any of the traversal storage banks; an arbiter/allocator to control the point-to-point switch matrix to establish a particular group of interconnections between the cache banks and the traversal storage banks in a given clock cycle.

First claim

What is claimed is:

1. An apparatus comprising:
ray traversal hardware logic to perform traversal operations to traverse rays through a bounding volume hierarchy (BVH) comprising a plurality of BVH nodes, the ray traversal hardware logic comprising a plurality of traversal storage banks to store traversal data associated with the BVH nodes and/or the rays as the ray traversal hardware logic performs the traversal operations; and
a cache comprising a plurality of cache banks to store the traversal data prior to being moved into the traversal storage banks for processing by the ray traversal hardware logic; and
an inter-bank interconnect comprising:
a point-to-point switch matrix to couple any of the cache banks to any of the traversal storage banks;
an arbiter/allocator to control the point-to-point switch matrix to establish a particular group of interconnections between the cache banks and the traversal storage banks in a given clock cycle.

2. The apparatus of claim 1 wherein the arbiter/allocator is to control the switch matrix to establish a particular group of interconnections between the cache banks and the traversal storage banks in accordance with an arbitration matrix.

3. The apparatus of claim 2 wherein the arbitration matrix comprises a plurality of rows corresponding to the plurality of cache banks and a plurality of columns corresponding to the traversal storage banks.

4. The apparatus of claim 3 wherein the arbitration matrix is to store a first value in a first row and first column to indicate that an interconnect is to be formed between a first cache bank associated with the first row and a first traversal storage bank associated with the first column.

5. The apparatus of claim 2 wherein the arbiter/allocator is a diagonal priority arbiter (DPA) which performs diagonal priority arbitration using values in the arbitration matrix.

6. The apparatus of claim 1 further comprising:
a cache/memory subsystem to identify traversal data requested by the traversal hardware logic within a first cache bank of the plurality of cache banks and to notify the arbiter/allocator of the traversal data stored in the first cache bank.

7. The apparatus of claim 6 wherein the arbiter/allocator is to responsively couple the first cache bank to a first traversal storage bank of the plurality of traversal storage banks over the point-to-point switch matrix.

8. The apparatus of claim 7 wherein the point-to-point switch matrix comprises a non-blocking crossbar switch.

9. The apparatus of claim 1 wherein the plurality of cache banks comprise N cache banks and the plurality of traversal storage banks comprise M traversal storage banks, wherein N and M are integer values and N can be equal to M.

10. A method comprising:
performing, by ray traversal hardware logic, traversal operations to traverse rays through a bounding volume hierarchy (BVH) comprising a plurality of BVH nodes, the ray traversal hardware logic comprising a plurality of traversal storage banks to store traversal data associated with the BVH nodes and/or the rays as the ray traversal hardware logic performs the traversal operations; and
storing, in a cache comprising a plurality of cache banks, the traversal data prior to being moved into the traversal storage banks for processing by the ray traversal hardware logic; and
interconnecting, by a point-to-point switch matrix, any of the cache banks to any of the traversal storage banks in accordance with control signals from an arbiter/allocator, the arbiter/allocator to establish a particular group of interconnections between the cache banks and the traversal storage banks in a given clock cycle.

11. The method of claim 10 wherein the arbiter/allocator is to control the switch matrix to establish a particular group of interconnections between the cache banks and the traversal storage banks in accordance with an arbitration matrix.

12. The method of claim 11 wherein the arbitration matrix comprises a plurality of rows corresponding to the plurality of cache banks and a plurality of columns corresponding to the traversal storage banks.

13. The method of claim 12 wherein the arbitration matrix is to store a first value in a first row and first column to indicate that an interconnect is to be formed between a first cache bank associated with the first row and a first traversal storage bank associated with the first column.

14. The method of claim 11 wherein the arbiter/allocator is a diagonal priority arbiter (DPA) which performs diagonal priority arbitration using values in the arbitration matrix.

15. The method of claim 10 further comprising:
identifying traversal data requested by the traversal hardware logic within a first cache bank of the plurality of cache banks and to notifying the arbiter/allocator of the traversal data stored in the first cache bank.

16. The method of claim 15 wherein the arbiter/allocator is to responsively couple the first cache bank to a first traversal storage bank of the plurality of traversal storage banks over the point-to-point switch matrix.

17. The method of claim 16 wherein the point-to-point switch matrix comprises a non-blocking crossbar switch.

18. The method of claim 10 wherein the plurality of cache banks comprise N cache banks and the plurality of traversal storage banks comprise M traversal storage banks, wherein N and M are integer values and N can be equal to M.

19. A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:
performing, by ray traversal hardware logic, traversal operations to traverse rays through a bounding volume hierarchy (BVH) comprising a plurality of BVH nodes, the ray traversal hardware logic comprising a plurality of traversal storage banks to store traversal data associated with the BVH nodes and/or the rays as the ray traversal hardware logic performs the traversal operations; and
storing, in a cache comprising a plurality of cache banks, the traversal data prior to being moved into the traversal storage banks for processing by the ray traversal hardware logic; and
interconnecting, by a point-to-point switch matrix, any of the cache banks to any of the traversal storage banks in accordance with control signals from an arbiter/allocator, the arbiter/allocator to establish a particular group of interconnections between the cache banks and the traversal storage banks in a given clock cycle.

20. The non-transitory machine-readable medium of claim 19 wherein the arbiter/allocator is to control the switch matrix to establish a particular group of interconnections between the cache banks and the traversal storage banks in accordance with an arbitration matrix.

21. The non-transitory machine-readable medium of claim 20 wherein the arbitration matrix comprises a plurality of rows corresponding to the plurality of cache banks and a plurality of columns corresponding to the traversal storage banks.

22. The non-transitory machine-readable medium of claim 21 wherein the arbitration matrix is to store a first value in a first row and first column to indicate that an interconnect is to be formed between a first cache bank associated with the first row and a first traversal storage bank associated with the first column.

23. The non-transitory machine-readable medium of claim 22 wherein the arbiter/allocator is a diagonal priority arbiter (DPA) which performs diagonal priority arbitrati

Assignees

• Intel Corp

Inventors

• Norris Michael
• Appu Abhishek R
• Surti Prasoonkumar
• Vaidyanathan Karthik

Classifications

• G06T1/60 Primary

  Memory management · CPC title

• G06T15/06 Primary

  Ray-tracing · CPC title

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F12/0813

  with a network or matrix configuration · CPC title