Method for mapping an input vector to an output vector by means of a matrix circuit

Patent metadata

Field	Value
Publication number	US-12450307-B2
Application number	US-202318532826-A
Country	US
Kind code	B2
Filing date	Dec 7, 2023
Priority date	Dec 7, 2022
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

The disclosure relates to a method for mapping an input vector to an output vector by means of a matrix circuit which has memory cells arranged in a matrix in a plurality of rows and a plurality of columns and first, second and third lines, each memory cell having an adjustable memory state, is connected to the first line ( 22 ) of the corresponding row, is connected to the second and third lines of the corresponding column and is set up to generate an electrical current (I 1 , I 2 , I 3 ) depending on the memory state and voltages applied to the first, second and third lines, is connected to the second and third lines of the corresponding column and is arranged to conduct an electric current (I 1 , I 2 , I 3 ) into the third line ( 26 ) as a function of the memory state and voltages applied to the first, second and third lines, each memory cell having a semiconductor switching element ( 28 ) with a control terminal which is connected to the second line ( 24 ) of the corresponding column; wherein input voltages (U 1 , U 2 , U 3 ) corresponding to components of the input vector are applied ( 110 ) to the first lines; wherein for each column: a ramp voltage (V 1 , V 2 , V 3 ) is applied ( 120 ) to the second line assigned to the column, the level of which is increased with time ( 130 ); a total current is detected at the third line assigned to the column and a time period elapsed since a start time of the level increase of the corresponding ramp voltage is determined ( 150 ) until the magnitude of the total current reaches a certain current magnitude threshold (Ig) ( 140 ); and a component of the output vector corresponding to the column is determined ( 170 ) based on the elapsed time period (t 1 , t 2 , t 3 ).

First claim

The invention claimed is:

1. A method of mapping an input vector to an output vector by means of a matrix circuit, which has first lines, second lines, third lines, and memory cells arranged in a matrix in a plurality of rows and a plurality of columns,
wherein each of the first lines is assigned to a respective row of the plurality of rows, each of the second lines is assigned to a respective column of the plurality of columns, and each of the third lines is assigned to a respective column of the plurality of columns,
wherein input voltages corresponding to components of the input vector are applied to the first lines,
wherein each memory cell
has an adjustable memory state,
is connected to one of the first lines assigned to the row in which the memory cell is located,
is connected to one of the second lines assigned to the column in which the memory cell is located,
is connected to one of the third lines assigned to the column in which the memory cell is located,
is configured to conduct an electric current from the one of the first lines to the one of the third lines as a function of the adjustable memory state and of voltages applied to the one of the first lines, the one of the second lines, and the one of the third lines, and
comprises a semiconductor switching element having a control terminal connected to the one of the second lines assigned to the column in which the semiconductor switching element is located,
the method comprising the following steps for each column:
applying a respective ramp voltage to the second line assigned to the column;
increasing the level of the respective ramp voltage over time;
detecting a respective total current at the third line assigned to the column;
determining a respective time period that has elapsed from a start time of the step of increasing the level of the respective ramp voltage until a respective certain current magnitude threshold is reached by a magnitude of the respective total current; and
determining a respective component of the output vector corresponding to the column based on the respective time period.

2. The method according to claim 1 , wherein each of the semiconductor switching elements of the matrix has a respective adjustable threshold voltage, and the adjustable memory state of a memory cell is dependent on the respective adjustable threshold voltage.

3. The method according to claim 1 , further comprising for each column, terminating the step of increasing the level of the respective ramp voltage when the respective certain current magnitude threshold is reached.

4. The method according to claim 1 , further comprising, for each column, terminating the step of applying the respective ramp voltage when the respective certain current magnitude threshold is reached.

5. The method according to claim 1 , further comprising beginning the step of increasing the level of the respective ramp voltage at several columns at a same starting time.

6. The method according to claim 1 , wherein a rate of increasing the level of the respective ramp voltage at several columns is a same rate.

7. The method according to claim 1 , wherein the input voltages are proportional to the components of the input vector, and each determined component of the output vector is proportional to a corresponding column's determined respective time period.

8. The method according to claim 1 , further comprising setting the memory states of the memory cells according to matrix elements of a predetermined matrix.

9. The method according to claim 1 , wherein each determined respective time period is based on a number of elapsed clock cycles.

10. A circuit comprising
a matrix circuit, which has first lines, second lines, third lines, and memory cells arranged in a matrix in a plurality of rows and a plurality of columns,
wherein each of the first lines is assigned to a respective row of the plurality of rows, each of the second lines is assigned to a respective column of the plurality of columns, and each of the third lines is assigned to a respective column of the plurality of columns,
wherein each memory cell
has an adjustable memory state,
is connected to one of the first lines assigned to the row in which the memory cell is located,
is connected to one of the second lines assigned to the column in which the memory cell is located,
is connected to one of the third lines assigned to the column in which the memory cell is located,
is configured to conduct an electric current from the one of the first lines to the one of the third lines as a function of the adjustable memory state and of voltages applied to the one of the first lines, the one of the second lines, and the one of the third lines, and
comprises a semiconductor switching element having a control terminal connected to the one of the second lines assigned to the column in which the semiconductor switching element is located, and

a controller configured to perform the following steps for each column:
apply a respective ramp voltage to the second line assigned to the column;
increase the level of the respective ramp voltage over time;
detect a respective total current at the third line assigned to the column;
determine a respective time period that has elapsed from a start time of the increasing the level of the respective ramp voltage until a respective certain current magnitude threshold is reached by the magnitude of the respective total current; and
determine a respective component of the output vector corresponding to the column based on the respective time period.

11. The circuit according to claim 10 , wherein each of the semiconductor switching elements is a ferroelectric field-effect transistor having a respective adjustable threshold voltage, wherein the adjustable memory state of the memory cell comprising the semiconductor switching element depends on the respective adjustable threshold voltage.

12. The circuit according to claim 10 , wherein each of the memory cells comprises a memristor and/or resistor, wherein the adjustable memory state of the respective memory cell depends on a resistance value of the memristor or the resistor.

13. The circuit according to claim 10 , wherein each of the semiconductor switching elements comprises a drain terminal and a source terminal, wherein the drain terminal is connected to the first line assigned to the row in which the respective semiconductor switching element is located, and the source terminal is connected to the third line assigned to the column in which the respective semiconductor switching element is located.

14. The circuit according to claim 10 , further comprising one or more ramp generators connected to the second lines and configured to perform the step of increase the level of the respective ramp voltage.

15. The circuit according to claim 10 , further comprising current-voltage converters connected to the third lines and comparators connected downstream of these, which are set up to compare output voltages of transimpedance amplifiers with voltage thresholds corresponding to the certain respective current magnitude thresholds.

Assignees

• Bosch Gmbh Robert
• Fraunhofer Ges Forschung

Inventors

• Kirchner Tobias
• Soliman Taha
• Kaempfe Thomas

Classifications

• G06F2207/4824

  Neural networks · CPC title

• G06F7/5443

  Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00) · CPC title

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title

• G06N3/063

  using electronic means · CPC title

• G06F17/153

  Multidimensional correlation or convolution · CPC title