Device and methods for communication between electronic components

Patent metadata

Field	Value
Publication number	US-12450184-B2
Application number	US-202418632143-A
Country	US
Kind code	B2
Filing date	Apr 10, 2024
Priority date	May 5, 2023
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

A system may include a communication circuit as part of a microcontroller. One or more registers may be configured to enable communication between the communication circuit and one or more external peripherals without a CPU or other processor controlling the communication. The one or more registers may be configured to allow a specific trigger event to initiate communication between the communication circuit and the external peripheral. A DMA controller may transmit data from the communication circuit to a memory and may transmit data from the memory to the external peripheral.

First claim

The invention claimed is:

1. A device comprising:
a microcontroller comprising a communication circuit, a central processing unit (CPU), a direct-memory access (DMA) controller and a memory, the communication circuit coupled to the CPU, the DMA controller and an external peripheral, the communication circuit comprising:
a trigger configuration register to store trigger configuration settings;
an address configuration register to store an address of the external peripheral;
a count configuration register to store a numerical value;
at least one trigger input;

wherein the communication circuit:
enters a peripheral communication mode based on the trigger configuration settings and a trigger event on the at least one trigger input;
transfers a number of bytes between the communication circuit and the external peripheral addressed by the address stored in the address configuration register, the number of bytes transferred based on the numerical value stored in the count register;
exits the peripheral communication mode based on completion of the transfer of the number of bytes and based on the trigger configuration settings, and

the DMA controller to transfer data between the communication circuit and the memory.

2. The device as claimed in claim 1 , the trigger configuration settings comprising a trigger enable setting, a trigger source setting, a read/write select setting, a stop/restart condition setting, and an end event output setting.

3. The device as claimed in claim 2 , the end event output setting to specify one or more interrupt outputs comprising at least one of a transmit register empty interrupt, a receive register full interrupt, and a message complete interrupt.

4. The device as claimed in claim 1 , the communication circuit comprising a chip select configuration register.

5. The device as claimed in claim 1 , the DMA controller to transfer data between the communication circuit and one or more general purpose registers within the microcontroller.

6. The device as claimed in claim 1 , wherein transfers a number of bytes comprises reading a number of bytes from the external peripheral.

7. The device as claimed in claim 1 , wherein transfers a number of bytes comprises writing a number of bytes to the external peripheral.

8. A communication system comprising:
an external peripheral;
a microcontroller coupled to the external peripheral, the microcontroller comprising a communication circuit, a CPU, a DMA controller and a memory, the communication circuit to couple to the CPU and the DMA controller, the communication circuit comprising:
a trigger configuration register to store trigger configuration settings;
an address configuration register to store an address of the external peripheral;
a count register to store a numerical value;
at least one trigger input;

wherein the communication circuit:
enters a peripheral communication mode based on trigger configuration settings in the trigger configuration register and a trigger event on the at least one trigger input;
transfers a number of bytes between the communication circuit and the external peripheral addressed by the address stored in the address configuration register, the number of bytes transferred based on the numerical value stored in the count register;
exits the peripheral communication mode based on configuration settings in the trigger configuration register, and

the DMA controller to transfer data between the communication circuit and a memory.

9. The system as claimed in claim 8 , the trigger configuration settings comprising a trigger enable setting, a trigger source setting, a read/write select setting, a stop/restart condition setting, and an end event output setting.

10. The system as claimed in claim 9 , the end event output setting to specify one or more interrupt outputs comprising at least one of a transmit register empty interrupt, a receive register full interrupt, and a message complete interrupt for triggering DMA transfers.

11. The system as claimed in claim 8 , the communication circuit comprising a chip select configuration register.

12. The system as claimed in claim 8 , the DMA controller to transfer data between the communication circuit and one or more general purpose registers within the microcontroller.

13. The system as claimed in claim 8 , the DMA controller configured to transfer data from a source address to a destination address.

14. A method for communication with an external peripheral comprising:
writing to one or more configuration registers in a communication circuit;
configuring a DMA controller to transfer data between the communication circuit and a memory;
receiving a trigger signal at the communication circuit, the trigger signal specified by values stored in at least one of the configuration registers;
transferring data between an external peripheral and the communication circuit, the address of the external peripheral based upon a value stored in at least one the configuration registers, and the number of bytes of data to transfer based on a numerical value stored in at least one of the configuration registers;
terminating the communication based upon completion of the transferring of data and based on a value stored in at least one of the configuration registers, and
transferring data between the communication circuit and the memory based on the configuration of the DMA controller.

15. The method as claimed in claim 14 , the configuration registers comprising one or more trigger configuration registers, one or more address configuration registers, and one or more count registers.

16. The method as claimed in claim 14 , the configuration registers comprising one or more chip select configuration registers.

17. The method as claimed in claim 14 , the trigger configuration registers comprising a trigger enable setting, a trigger source setting, a read/write select setting, a stop/restart condition setting, and an end event output setting.

18. The method as claimed in claim 17 , the end event output setting to specify one or more interrupt outputs comprising at least one of a transmit register empty interrupt, a receive register full interrupt, and a message complete interrupt for triggering DMA transfers.

19. The method as claimed in claim 14 , the DMA controller to transfer data between the communication circuit and one or more general purpose registers within the microcontroller.

Assignees

• Microchip Tech Inc

Inventors

• Curtis Keith

Classifications

• G06F13/409

  Mechanical coupling (back panels H05K7/1438) · CPC title

• G06F13/24

  using interrupt (G06F13/32 takes precedence) · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title