PASID granularity resource control for IOMMU

US12449976B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12449976-B2
Application numberUS-202318239363-A
CountryUS
Kind codeB2
Filing dateAug 29, 2023
Priority dateMar 25, 2021
Publication dateOct 21, 2025
Grant dateOct 21, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An embodiment of an integrated circuit may comprise memory to store respective resource control descriptors in correspondence with respective identifiers, and an input/output (IO) memory management unit (IOMMU) communicatively coupled to the memory, the IOMMU including circuitry to determine resource control information for an IO transaction based on a resource control descriptor stored in the memory that corresponds to an identifier associated with the IO transaction, and control utilization of one or more resources of the IOMMU based on the determined resource control information. Other embodiments are disclosed and claimed.

First claim

Opening claim text (preview).

What is claimed is: 1. An integrated circuit, comprising: memory to store: one or more virtualization tables comprising resource control descriptors which each correspond to one of a respective process address space identifier (PASID) or a respective domain identifier, the resource control descriptors each to identify a respective one or more quality of service (QOS) requirements; and a table comprising a first plurality of entries each indexed by a respective PASID; and an input/output (IO) memory management unit (IOMMU) communicatively coupled to the memory, the IOMMU including circuitry to: receive an indication of an IO transaction which is to access one or more shared resources; determine, based on the indication, an identifier of a requester of the IO transaction; perform a search of the table based on the identifier of the requester, to identify a first entry of the first plurality of entries; perform an evaluation to determine whether the first entry includes a field that is to provide a pointer to a resource control descriptor; where the evaluation determines that the first entry includes the field: determine, based on a value at the field, a first one or more QoS requirements identified by one of the resource control descriptors; and control a performance of the IO transaction according to the first one or more QoS requirements; and where the evaluation fails to determine that the first entry includes the field: determine, based on a domain identifier which corresponds to the requester, a second one or more QoS requirements identified by another of the resource control descriptors; and control the performance of the IO transaction according to the second one or more QoS requirements. 2. The integrated circuit of claim 1 , wherein the first one or more QoS requirements comprises multiple one or more QoS requirements. 3. The integrated circuit of claim 1 , wherein the identifier of the requester comprises a bus number, a device number, and a function number, and a PASID number. 4. The integrated circuit of claim 1 , wherein the circuitry is to: determine if a PASID-granularity control is disabled; and, if so determined, determine the second one or more QoS requirements based on the domain identifier. 5. The integrated circuit of claim 1 , wherein the first one or more QoS requirements comprise a threshold for a number of entries for the identifier in an IO translation lookaside buffer (IOTLB), and wherein, in response to an IOTLB miss for the IO transaction, the circuitry is further to: determine if a count of entries in the IOTLB associated with the identifier exceeds the threshold for the number of entries for the identifier in the IOTLB; and, if so determined, identify a least recently used entry in the IOTLB associated with the identifier and invalidate the identified entry. 6. The integrated circuit of claim 1 , wherein the first one or more QoS requirements comprise a threshold for a number of inflight page requests for the identifier, and wherein, in response to a page request for the IO transaction, the circuitry is further to: determine if a count of inflight page requests associated with the identifier exceeds the threshold for the number of inflight page requests for the identifier; and, if so determined, reject the page request associated with the identifier. 7. A method, comprising: storing one or more virtualization tables comprising resource control descriptors which each correspond to one of a respective process address space identifier (PASID) or a respective domain identifier, the resource control descriptors each to identify a respective one or more quality of service (QOS) requirements; storing a table comprising a first plurality of entries each indexed by a respective PASID; receiving an indication of an input/output (IO) transaction which is to access one or more shared resources; determining, based on the indication, an identifier of a requester of the IO transaction; performing a search of an IO memory management unit (IOMMU) table, based on identifier of the requester, to identify a first entry of the first plurality of entries; performing an evaluation to determine whether the first entry includes a field that is to provide a pointer to a resource control descriptor; where the evaluation determines that the first entry includes the field: determining, based on a value at the field, a first one or more QoS requirements identified by one of the resource control descriptors; and controlling a performance of the IO transaction according to the first one or more QoS requirements; and where the evaluation fails to determine that the first entry includes the field: determining, based on a domain identifier which corresponds to the requester, a second one or more QoS requirements identified by another of the resource control descriptors; and controlling the performance of the IO transaction according to the second one or more QoS requirements. 8. The method of claim 7 , wherein the first one or more QoS requirements comprises multiple one or more QoS requirements. 9. The method of claim 7 , wherein the identifier of the requester comprises a bus number, a device number, and a function number, and a PASID number. 10. The method of claim 7 , further comprising: determining if a PASID-granularity control is disabled; and, if so determined, determining the second one or more QoS requirements based on the domain identifier. 11. The method of claim 7 , wherein the first one or more QoS requirements comprise a threshold for a number of entries in an IO translation lookaside buffer (IOTLB) for the identifier, and wherein, in response to an IOTLB miss for the IO transaction, the method further comprises: determining if a count of entries in the IOTLB associated with the identifier exceeds the threshold for the number of entries in the IOTLB for the identifier; and, if so determined, identifying a least recently used entry in the IOTLB associated with the identifier and invalidating the identified entry. 12. The method of claim 7 , wherein the first one or more QoS requirements comprise a threshold for a number of inflight page requests for the identifier, and wherein, in response to a page request for the IO transaction, the method further comprises: determining if a count of inflight page requests associated with the identifier exceeds the threshold for the number of inflight page requests for the identifier; and, if so determined, rejecting the page request associated with the identifier. 13. An apparatus, comprising: a core; a memory management unit (MMU) communicatively coupled to the core; memory communicatively coupled to the MMU to store: one or more virtualization tables comprising resource control descriptors which each correspond to one of a respective process address space identifier (PASID) or a respective domain identifier, the resource control descriptors each to identify a respective one or more quality of service (QOS) requirements; and a table comprising a first plurality of entries each indexed by a respective PASID; and an input/output (IO) memory management unit (IOMMU) communicatively coupled to the memory, the IOMMU including circuitry to: receive an indication of an IO transaction which is to access one or more shared resources; determine, based on the indication, an identifier of a requester of the IO transaction; perform a search of the table based on the identifier of the requester, to identify a first entry of the first plurality of entries; perform an evaluation to determine whether the first entry includes a field that is to provide a p

Assignees

Inventors

Classifications

  • Single storage device · CPC title

  • Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

  • G06F3/061Primary

    Improving I/O performance · CPC title

  • for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

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What does patent US12449976B2 cover?
An embodiment of an integrated circuit may comprise memory to store respective resource control descriptors in correspondence with respective identifiers, and an input/output (IO) memory management unit (IOMMU) communicatively coupled to the memory, the IOMMU including circuitry to determine resource control information for an IO transaction based on a resource control descriptor stored in the …
Who is the assignee on this patent?
Intel Corp
What technology area does this patent fall under?
Primary CPC classification G06F3/061. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 21 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).