Exiting of low power modes of redrivers and retimers

Patent metadata

Field	Value
Publication number	US-12449878-B2
Application number	US-202318241833-A
Country	US
Kind code	B2
Filing date	Sep 1, 2023
Priority date	Sep 1, 2023
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

This application is directed to controlling a low power mode of a data communication channel. An electronic device includes an input interface for receiving an input signal. A signal conditioning circuit is coupled to the input interface, and configured to be disabled and consume power below a first threshold power level in a low power mode. A first signal detector is coupled to the signal conditioning circuit, and a second signal detector is coupled to the first signal detector. The first signal detector is configured to monitor a differential mode component of the input signal for controlling the signal conditioning circuit to exit the low power mode. The second signal detector is configured to, in the low power mode, detect a start of the input signal and enable the first signal detector based on a common mode component of the input signal.

First claim

What is claimed is:

1. An electronic device, comprising:
an input interface for receiving an input signal;
a signal conditioning circuit coupled to the input interface, wherein the signal conditioning circuit is configured to be disabled and consume power below a first threshold power level in a low power mode;
a first signal detector coupled to the signal conditioning circuit, wherein the first signal detector is configured to monitor a differential mode component of the input signal for controlling the signal conditioning circuit to exit the low power mode; and
a second signal detector coupled to the first signal detector, the second signal detector configured to, in the low power mode, detect a start of the input signal and enable the first signal detector based on a common mode component of the input signal.

2. The electronic device of claim 1 , wherein the common mode component has a common mode frequency that is lower than a first threshold frequency, and the differential mode component has a differential frequency that is higher than a second threshold frequency that is greater than the first threshold frequency.

3. The electronic device of claim 1 , wherein the first signal detector is configured to be disabled and consume power below a second threshold power level before the second signal detector enables the first signal detector in the low power mode.

4. The electronic device of claim 1 , wherein the second signal detector is configured to, in the low power mode, detect the start of the input signal in accordance with a determination that the common mode component of the input signal changes by more than a threshold variation and reaches a common mode voltage.

5. The electronic device of claim 1 , wherein the first signal detector is further configured to determine whether the differential mode component of the input signal satisfies a low power exiting condition.

6. The electronic device of claim 5 , further comprising:
a power controller coupled to the first signal detector, the second signal detector, and the signal conditioning circuit, the power controller configured to control the signal conditioning circuit to exit the low power mode in accordance with a determination that the differential mode component of the input signal satisfies the low power exiting condition.

7. The electronic device of claim 5 , further comprising:
a power controller coupled to the first signal detector, the second signal detector, and the signal conditioning circuit, the power controller configured to keep the signal conditioning circuit in the low power mode in accordance with a determination that the differential mode component of the input signal does not satisfy the low power exiting condition.

8. The electronic device of claim 5 , wherein, in accordance with the low power exiting condition, the differential mode component is greater than a threshold differential level for at least a first predefined extended duration of time.

9. The electronic device of claim 1 , further comprising:
a power controller coupled to the first signal detector and the second signal detector, the power controller configured to receive a start detection signal indicating the start of the input signal from the second signal detector and enable the first signal detector in response to the start detection signal.

10. The electronic device of claim 1 , wherein:
the input signal includes a pair of differential input signals;
the common mode component of the input signal corresponds to an average of the pair of differential input signals; and
the differential mode component of the input signal includes a difference of the pair of differential input signals.

11. The electronic device of claim 1 , wherein the signal conditioning circuit includes a retimer of a data interface, and the data interface is configured to comply with a high-speed data communication protocol selected from the group consisting of: Universal Serial Bus (USB), DisplayPort (DP), and High-Definition Multimedia Interface (HDMI).

12. A controller circuit for controlling a signal conditioning circuit, comprising:
an input interface for receiving an input signal;
a first signal detector coupled to the signal conditioning circuit, wherein the first signal detector is configured to monitor a differential mode component of the input signal for controlling the signal conditioning circuit to exit a low power mode, and the signal conditioning circuit is configured to be disabled and consume power below a first threshold power level in the low power mode; and
a second signal detector coupled to the first signal detector, the second signal detector configured to, in the low power mode, detect a start of the input signal and enable the first signal detector based on a common mode component of the input signal.

13. The controller circuit of claim 12 , wherein the signal conditioning circuit has an operating mode in addition to the low power mode, and the signal conditioning circuit is configured to start and exit the operating mode based on the differential mode component of the input signal.

14. The controller circuit of claim 13 , wherein the first signal detector is configured to detect an absence of the differential mode component of the input signal in the operating mode, and the signal conditioning circuit is configured to exit the operating mode and start the low power mode in response to detection of the absence of the differential mode component of the input signal.

15. The controller circuit of claim 14 , wherein the first signal detector is configured to detect the absence of the differential mode component of the input signal, in accordance with a determination that the differential mode component is lower than a threshold differential level for at least a second extended duration of time.

16. The controller circuit of claim 13 , further comprising:
a power controller coupled to the second signal detector and the signal conditioning circuit, the power controller configured to control the signal conditioning circuit to exit the operating mode in response to detection of the absence of the differential mode component of the input signal.

17. A method for controlling a data interface, comprising, at an electronic device having a first signal detector and a second signal detector:
disabling at least part of a signal conditioning circuit in a lower power mode to control power consumption below a first threshold power level;
monitoring an input interface for receiving an input signal by the second signal detector;
based on a common mode component of the input signal, detecting a start of the input signal and enabling the first signal detector;
monitoring a differential mode component of the input signal by the first signal detector; and
based on the differential mode component, controlling the signal conditioning circuit to exit the low power mode.

18. The method of claim 17 , wherein the input interface is coupled to a processor of the electronic device and the input signal is from the processor.

19. The method of claim 17 , wherein the input interface is coupled to an external load device of the electronic device and the input signal is received from the external load device.

20. The method of claim 17 , wherein:
the input signal includes a pair of differential input signals;
the common mode component of the input signal includes an average of the pair of differential input signals; and
the differential mode component of the input signal includes a difference of th

Assignees

• Parade Tech Ltd

Inventors

• Gao Mengchuan
• Wang Hongquan
• Zhang Shengyuan
• Chen Yuanping
• Li Jianhong

Classifications

• G06F1/32 Primary

  Means for saving power · CPC title