Method of manufacturing a display apparatus

Patent metadata

Field	Value
Publication number	US-12446435-B2
Application number	US-202318342091-A
Country	US
Kind code	B2
Filing date	Jun 27, 2023
Priority date	Sep 27, 2019
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A display apparatus includes a buffer layer on a substrate, a first hole penetrating the buffer layer and exposing a portion of the substrate, a display layer with display elements and bypass lines on the buffer layer, a second hole penetrating the display layer and connected to the first hole, and an encapsulation member covering the display elements and the bypass lines. The bypass lines are configured to extend along a portion of a perimeter of the second hole and are disposed between the second hole and the display elements. At least a portion of an upper surface of the buffer layer is exposed by the second hole.

First claim

What is claimed is:

1. A method of manufacturing a display apparatus, the method comprising:
forming a buffer layer on a substrate;
forming a first hole penetrating the buffer layer and exposing a portion of the substrate;
forming a display layer on the buffer layer, the display layer comprising display elements and bypass lines;
forming a second hole penetrating the display layer, wherein the second hole is connected to the first hole and concentric thereto; and
forming an encapsulation member to cover the display layer,
wherein at least a portion of an upper surface of the buffer layer is exposed by the second hole, and
wherein the first hole is formed after the second hole is formed.

2. The method of claim 1 ,
wherein a first width of the first hole is less than a second width of the second hole.

3. The method of claim 1 ,
wherein the display layer comprises a first inorganic insulating layer and a first organic insulating layer,
wherein the forming of the second hole comprises:
forming a third hole penetrating the first inorganic insulating layer; and
forming a fourth hole penetrating the first organic insulating layer,
wherein each of the third hole and the fourth hole is concentric to the first hole, and
wherein at least a portion of an upper surface of the first inorganic insulating layer is exposed by the fourth hole.

4. The method of claim 3 ,
wherein the first hole is formed after the third hole is formed.

5. The method of claim 3 ,
wherein the fourth hole is formed after the third hole is formed.

6. The method of claim 3 ,
wherein the forming of the display layer comprises:
forming a semiconductor layer on the buffer layer;
forming the first inorganic insulating layer on the semiconductor layer;
forming a first contact hole in the first inorganic insulating layer to expose the semiconductor layer,
wherein the forming of the first contact hole and the forming of the third hole are simultaneously performed.

7. The method of claim 6 ,
wherein the forming of the display layer comprises:
forming a source electrode or a drain electrode connected to the semiconductor layer through the first contact hole;
forming the first organic insulating layer on the source electrode or the drain electrode; and
forming a second contact hole in the first organic insulating layer to expose the source electrode or the drain electrode,
wherein the forming of the second contact hole and the forming of the fourth hole are simultaneously performed.

8. The method of claim 1 , further comprising:
forming a metal layer and an input sensing section on the encapsulation member to overlap the bypass lines, wherein the input sensing section comprising a sensing electrode and an insulating layer;
forming a metal hole penetrating the metal layer,
wherein the sensing electrode is on a first surface of the insulating layer, and
wherein the metal layer is on a second surface, opposite to the first surface, of the insulating layer and electrically insulated from the sensing electrode, a width of the first hole is less than a width of the metal hole.

9. The method of claim 1 , further comprising:
forming a filler between the substrate and the encapsulation member and filling the first hole and the second hole.

10. The method of claim 9 ,
forming a spacer with an opening between the display layer and the encapsulation member,
wherein the forming of the filler further includes filling the opening of the spacer.

11. The method of claim 1 ,
wherein the forming of the first hole is performed such that the first hole is closed off at a bottom thereof by the portion of the substrate.

12. A method of manufacturing an electronic device, the method comprising:
forming a buffer layer on a substrate;
forming a first hole penetrating the buffer layer and exposing a portion of the substrate;
forming a display layer on the buffer layer, the display layer comprising display elements and bypass lines;
forming a second hole penetrating the display layer, wherein the second hole is connected to the first hole and concentric thereto; and
forming an encapsulation member to cover the display layer,
wherein at least a portion of an upper surface of the buffer layer is exposed by the second hole, and
wherein the first hole is formed after the second hole is formed.

13. The method of claim 12 ,
wherein a first width of the first hole is less than a second width of the second hole.

14. The method of claim 12 ,
wherein the display layer comprises a first inorganic insulating layer and a first organic insulating layer,
wherein the forming of the second hole comprises:
forming a third hole penetrating the first inorganic insulating layer; and
forming a fourth hole penetrating the first organic insulating layer,
wherein each of the third hole and the fourth hole is concentric to the first hole, and
wherein at least a portion of an upper surface of the first inorganic insulating layer is exposed by the fourth hole.

15. The method of claim 14 ,
wherein the first hole is formed after the third hole is formed.

16. The method of claim 14 ,
wherein the fourth hole is formed after the third hole is formed.

17. The method of claim 14 ,
wherein the forming of the display layer comprises:
forming a semiconductor layer on the buffer layer;
forming the first inorganic insulating layer on the semiconductor layer;
forming a first contact hole in the first inorganic insulating layer to expose the semiconductor layer,
wherein the forming of the first contact hole and the forming of the third hole are simultaneously performed.

18. The method of claim 17 ,
wherein the forming of the display layer comprises:
forming a source electrode or a drain electrode connected to the semiconductor layer through the first contact hole;
forming the first organic insulating layer on the source electrode or the drain electrode; and
forming a second contact hole in the first organic insulating layer to expose the source electrode or the drain electrode,
wherein the forming of the second contact hole and the forming of the fourth hole are simultaneously performed.

19. The method of claim 12 , further comprising:
forming a metal layer and an input sensing section on the encapsulation member to overlap the bypass lines, wherein the input sensing section comprising a sensing electrode and an insulating layer;
forming a metal hole penetrating the metal layer,
wherein the sensing electrode is on a first surface of the insulating layer, and
wherein the metal layer is on a second surface, opposite to the first surface, of the insulating layer and electrically insulated from the sensing electrode, a width of the first hole is less than a width of the metal hole.

20. The method of claim 12 , further comprising:
forming a filler between the substrate and the encapsulation member and filling the first hole and the second hole.

Assignees

• Samsung Display Co Ltd

Inventors

• Jang Donghyeon
• Lee Wonse
• Kim Sukyoung
• Yoon Youngsoo
• In Yunkyeong
• Jeon Yujin
• Cha Hyunji

Classifications

• H10K77/10

  Substrates, e.g. flexible substrates · CPC title

• H10K59/873

  Encapsulations · CPC title

• H10K59/8723

  Vertical spacers, e.g. arranged between the sealing arrangement and the OLED · CPC title

• H10K59/8722

  Peripheral sealing arrangements, e.g. adhesives, sealants · CPC title

• H10K59/121

  characterised by the geometry or disposition of pixel elements · CPC title