Hybrid heterojunction solar cell, cell component and preparation method

Patent metadata

Field	Value
Publication number	US-12446353-B2
Application number	US-202418901554-A
Country	US
Kind code	B2
Filing date	Sep 30, 2024
Priority date	Dec 4, 2023
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

The present disclosure provides a hybrid heterojunction solar cell, a cell component, and a preparation method, the hybrid heterojunction solar cell comprises a semiconductor substrate having a substrate front surface and a substrate back surface opposite to each other, wherein the substrate front surface is close to a light-facing side of the cell and the substrate back surface is close to a backlight side of the cell; at least two composite layers located on one side of the substrate front surface, each composite layer includes a multi-layer structure of a tunneling layer and a doped polysilicon layer sequentially arranged in a direction gradually away from the substrate front surface. The hybrid heterojunction solar cell, cell component and a preparation method provided by this disclosure can achieve a stable passivation effect on the cell surface, reduce light absorption in the non-metallic areas of the cell, and achieve better process control at the same time.

First claim

The invention claimed is:

1. A method of preparing a hybrid heterojunction solar cell, comprising:
preparing a semiconductor substrate, the semiconductor substrate has a substrate front surface and a substrate back surface opposite to each other, wherein the substrate front surface is close to a light-facing side of the cell and the substrate back surface is close to a backlight side of the cell;
preparing at least two composite layers and a positive metal electrode on the substrate front surface sequentially, each composite layer includes a multi-layer structure of a tunneling layer and a doped polysilicon layer sequentially arranged in a direction gradually away from the substrate front surface; and
preparing an intrinsic amorphous silicon layer, a backside doped layer, a transparent conductive layer, and a back metal electrode on the substrate back surface sequentially, wherein the backside doped layer includes a single layer or a multi-layer structure composed of a doped amorphous silicon, nanocrystalline silicon and/or microcrystalline silicon,
wherein preparing the at least two composite layers further includes:
sequentially forming a first tunneling layer, a first doped polysilicon layer, a second tunneling layer and a second doped polysilicon layer on the substrate front surface;
laser scanning part of the second doped polysilicon layer to grow a silicon oxide film to obtain a first semi-finished cell, the first semi-finished cell has a plurality of spaced and adjacently arranged contact areas and non-contact areas on a side of the substrate front surface, wherein, the contact areas are scanned by the laser, and the non-contact areas are not scanned by the laser;
etching the first semi-finished cell by using an alkaline solution to remove the second doped polysilicon layer of the non-contact areas;
removing the silicon oxide film and the second tunneling layer of the non-contact areas, so that each of the contact areas includes two composite layers, and each of the non-contact areas only includes one composite layer.

2. The method according to claim 1 , further comprising, when preparing the semiconductor substrate, etching the semiconductor substrate by using an alkali solution to remove contaminants and form an antireflective texture structure.

3. The method according to claim 1 , wherein forming the first tunneling layer and the second tunneling layer each comprises thermal oxidation, and forming the first doped polysilicon layer and the second doped polysilicon layer each comprises LPCVD or PECVD method.

4. The method according to claim 3 , wherein when forming the first doped polysilicon layer and the second doped polysilicon layer, the method further includes forming a microcrystalline silicon layer first, and at a temperature of 800° C.-930° C., doping with a doping source of phosphorus, annealing and crystallizing the microcrystalline silicon layer to form the doped polysilicon layer.

5. The method according to claim 1 , further comprising using ALD or PECVD to prepare a dielectric antireflection layer on the substrate front surface, and the dielectric antireflection layer includes a single dielectric layer or a stacked dielectric layer composed of one or more dielectric materials among aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride and magnesium fluoride.

6. The method according to claim 5 , wherein a portion of the dielectric antireflection layer is located in the contact areas, further comprising laser scanning the part of the dielectric antireflection layer located in the contact areas to expose the second doped polysilicon layer in the contact areas, and preparing the positive metal electrode on the exposed second doped polysilicon layer.

Assignees

• Trina Solar Co Ltd

Inventors

• Liu Wei
• Hu Yunyun
• Chen Daming
• Wu Kuiyi

Classifications

• H10F77/315

  the coatings being antireflective or having enhancing optical properties · CPC title

• H10F71/1221

  comprising polycrystalline silicon · CPC title

• H10F77/1642

  including only Group IV materials · CPC title

• H10F71/121

  The active layers comprising only Group IV materials · CPC title

• H10F71/1224

  comprising microcrystalline silicon · CPC title