CMOS imaging sensor structure and manufacturing method therefor

Patent metadata

Field	Value
Publication number	US-12446336-B2
Application number	US-201917432930-A
Country	US
Kind code	B2
Filing date	Oct 14, 2019
Priority date	Feb 22, 2019
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A CMOS imaging sensor structure and a manufacturing method therefor. The CMOS imaging sensor structure comprises a pixel unit of the CMOS imaging sensor set on a semiconductor substrate, the pixel unit comprises a circuit device region and a first photosensitive region, the circuit device region is set on the frontside of the semiconductor substrate, the first photosensitive region is set correspondingly in the semiconductor substrate below the circuit device region, the circuit device region is isolated from the first photosensitive region by an isolation region, and the circuit device region is electrical connected with the first photosensitive region through a conductive trench, a fill factor of a photosensitive region is increased, and performances of a reading circuit is increased by a more optimized design scheme. A second photosensitive region of the pixel unit can also be set on the semiconductor substrate on a side of the circuit device region, thus a larger photosensitive region can be formed together with the first photosensitive region. The present invention also provides a manufacturing method for the CMOS imaging sensor structure.

First claim

What is claimed is:

1. A CMOS imaging sensor structure, comprising: a pixel unit of the CMOS imaging sensor set on a semiconductor substrate, the pixel unit comprises a circuit device region and a first photosensitive region, the circuit device region is set on the frontside of the semiconductor substrate, the first photosensitive region is set correspondingly in the semiconductor substrate below the circuit device region, the circuit device region is isolated from the first photosensitive region by an isolation region, and the circuit device region is electrically connected with the first photosensitive region through a conductive trench;
wherein, the semiconductor substrate is an SOI substrate, and the SOI substrate comprises a silicon substrate layer, a buried oxygen layer, and an epitaxial silicon layer sequentially, and the CMOS imaging sensor comprises:
the circuit device region set on the epitaxial silicon layer and the first photosensitive region set on the silicon substrate layer; the circuit device region is isolated from the first photosensitive region by the buried oxygen layer, and the circuit device region is electrically connected with the first photosensitive region through a conductive trench passing through the buried oxide layer;
each of pixels of the CMOS imaging sensor is set with the circuit device region and the first photosensitive region, the circuit device region and the first photosensitive region are set on the epitaxial silicon layer and the silicon substrate layer respectively, upper and lower positions of the circuit device region and the first photosensitive region are corresponding;
each of the pixels of the CMOS imaging sensor is isolated by a shallow trench isolation structure.

2. The CMOS imaging sensor structure of claim 1 , wherein, the shallow trench isolation structure comprises a first shallow trench isolation structure set on the epitaxial silicon layer and a second shallow trench isolation structure set on the silicon substrate layer.

3. The CMOS imaging sensor structure of claim 2 , wherein, the end of the first shallow trench isolation structure and the end of the second shallow trench isolation structure are connected together with the buried oxide layer, and other ends are exposed on a surface of the epitaxial silicon layer and a surface of the silicon substrate layer respectively.

4. The CMOS imaging sensor structure of claim 1 , wherein, the conductive trench passes through the buried oxide layer from the surface of the epitaxial silicon layer, and stops in the silicon substrate layer, and the conductive trench is connected with the circuit device region through a part of the conductive trench located in the epitaxial silicon layer, and connected with the first photosensitive region through a part of the conductive trench located in the silicon substrate layer.

5. The CMOS imaging sensor structure of claim 1 , wherein, the conductive trench is a metal conductive trench filled with a metal or a polysilicon conductive trench filled with polysilicon.

6. The CMOS imaging sensor structure of claim 5 , wherein, a metal silicide layer and a metal nitride layer are formed sequentially on inner walls of the metal conductive trench, and the metal conductive trench on the metal nitride layer is filled with an electrode metal.

7. The CMOS imaging sensor structure of claim 6 , wherein, the metal silicide layer is a titanium silicide layer or a tantalum silicide layer formed by a heating treatment of titanium or tantalum deposited on the inner walls of the metal conductive trench with silicon in the epitaxial silicon layer and the silicon substrate layer.

8. A CMOS imaging sensor structure, comprising: a pixel unit of the CMOS imaging sensor set on a semiconductor substrate, the pixel unit comprises a circuit device region and a first photosensitive region, the circuit device region is set on the frontside of the semiconductor substrate, the first photosensitive region is set correspondingly in the semiconductor substrate below the circuit device region, the circuit device region is isolated from the first photosensitive region by an isolation region, and the circuit device region is electrically connected with the first photosensitive region through a conductive trench;
wherein, the pixel unit is further set with a second photosensitive region, the second photosensitive region and the circuit device region are set on the frontside of the semiconductor substrate side by side; the first photosensitive region is connected with the circuit device region located above and the second photosensitive region located beside the conductive trench;
wherein, the circuit device region is isolated from the first photosensitive region located below through the isolation region, the periphery of the circuit device region and the second photosensitive region is set with a deep trench isolation structure to realize isolation between the pixels, upper and lower surfaces of the deep trench structure are exposed from the frontside and backside of the semiconductor substrate respectively;
wherein, a metal interconnection layer is set on the frontside of the semiconductor substrate, and lights are incident from the backside of the semiconductor substrate.

9. The CMOS imaging sensor structure of claim 8 , wherein, the first photosensitive region is formed with a first photosensitive PN device, the second photosensitive region is formed with a second photosensitive PN device, and the circuit device region is formed with a plurality of circuit devices, the first photosensitive PN device and the second photosensitive PN device are connected with a source/drain region of a corresponding circuit device in the circuit device region though the conductive trench.

10. The CMOS imaging sensor structure of claim 9 , wherein the conductive trench is located in the semiconductor substrate, upper surface and lower surface of the conductive trench are contacted with the second photosensitive PN device and the first photosensitive PN device respectively.

11. The CMOS imaging sensor structure of claim 8 , wherein, the conductive trench is filled with doped conductive polysilicon and performed with a diffusion treatment; the isolation region is an oxygen ion implanting isolation layer.

12. The CMOS imaging sensor structure of claim 8 , wherein, the lower surface of the deep trench isolation structure is exposed by thinning the backside of the semiconductor substrate.

13. The CMOS imaging sensor structure of claim 8 , wherein, the circuit device is a MOS transistor.

14. The CMOS imaging sensor structure of claim 13 , wherein, the metal interconnection layer is set in an interlayer dielectric layer on the frontside of the semiconductor substrate, and surface of the interlayer dielectric layer is set with a pad layer connected with the metal interconnection layer.

15. A manufacturing method for the CMOS imaging sensor structure according to claim 1 , comprising following steps:
providing an SOI substrate, which comprises a silicon substrate layer, a buried oxygen layer and an epitaxial silicon layer sequentially;
forming a first shallow trench isolation structure on the epitaxial silicon layer for isolating each of pixels of the CMOS imaging sensor, exposing upper surface of the first shallow trench isolation structure on surface of the epitaxial silicon layer, and connecting lower surface of the first shallow trench isolation structure with the buried oxygen layer;
forming a conductive trench in each of the pixels, which passing through the buried oxide layer from the surface of the epitaxial silicon layer and stopping in the silicon s

Assignees

• Shanghai Ic R&D Ct Co Ltd
• Shanghai Integrated Circuit Equipment & Mat Industry Innovation Center Co Ltd

Inventors

• Kang Xiaoxu
• Li Ming

Classifications

• H10F39/811

  Interconnections · CPC title

• H10F39/807

  Pixel isolation structures · CPC title

• H10F39/026 Primary

  Wafer-level processing · CPC title

• H10F39/18

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title

• H10F39/014

  of CMOS image sensors · CPC title