Capacitor, method of fabricating the capacitor, and electronic device including the capacitor

Patent metadata

Field	Value
Publication number	US-12446239-B2
Application number	US-202217861577-A
Country	US
Kind code	B2
Filing date	Jul 11, 2022
Priority date	Nov 9, 2021
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A capacitor includes a lower electrode including a perovskite material, an upper electrode spaced apart from the lower electrode, a dielectric layer positioned between the lower electrode and the upper electrode and including a perovskite material, and a passivation layer positioned between the lower electrode and the dielectric layer and including SrxTiyO3 in which a content of Ti is greater than a content of Sr.

First claim

What is claimed is:

1. A capacitor comprising:
a lower electrode comprising a perovskite material;
an upper electrode spaced apart from the lower electrode;
a dielectric layer between the lower electrode and the upper electrode and comprising a perovskite material; and
a passivation layer between the lower electrode and the dielectric layer and comprising Sr x Ti y O 3 in which a content of Ti is greater than a content of Sr.

2. The capacitor of claim 1 , wherein the content of Ti in the passivation layer is 55% to 70%.

3. The capacitor of claim 1 , wherein the lower electrode comprises one or more of SrVO 3 , SrMnO 3 , SrCrO 3 , SrFeO 3 , SrCoO 3 SrRuO 3 , SrMoO 3 , SrIrO 3 , SrNbO 3 , and SrCoO 3 .

4. The capacitor of claim 1 , wherein the lower electrode has a crystalline structure.

5. The capacitor of claim 1 , wherein the dielectric layer comprises SrTiO 3 .

6. The capacitor of claim 1 , wherein the dielectric layer has a crystalline structure.

7. The capacitor of claim 1 , wherein the dielectric layer comprises SrTiO 3 incorporating at least one of Ba and Y.

8. The capacitor of claim 1 , wherein a ratio of a thickness of the passivation layer to a total thickness of the dielectric layer and the passivation layer is 1/20 to ⅕.

9. The capacitor of claim 1 , wherein a total dielectric constant of the dielectric layer and the passivation layer is 60 to 80.

10. The capacitor of claim 1 , wherein the upper electrode comprises a perovskite material.

11. The capacitor of claim 1 , wherein the upper electrode comprises one or more of SrVO 3 , SrMnO 3 , SrCrO 3 , SrFeO 3 , SrCoO 3 SrRuO 3 , SrMoO 3 , SrIrO 3 , SrNbO 3 , and SrCoO 3 .

12. An electronic device comprising:
a transistor; and
the capacitor of claim 1 , the capacitor being electrically connected to the transistor.

13. The electronic device of claim 12 , wherein the transistor comprises:
a semiconductor substrate comprising a source region, a drain region, and a channel region between the source region and the drain region; and
a gate stack on the semiconductor substrate, facing the channel region, and comprising a gate insulating layer and a gate electrode.

14. The electronic device of claim 12 , further comprising:
a memory cell comprising the capacitor and the transistor; and
a controller electrically connected to the memory cell and configured to control the memory cell.

15. A method of fabricating a capacitor, the method comprising:
forming a lower electrode on a substrate, the lower electrode comprising a perovskite material;
forming a passivation layer on the lower electrode by using a first gas comprising Ti, a second gas comprising a hydroxyl group (OH), a third gas comprising an oxygen radical (O), and a fourth gas comprising Sr, wherein the passivation layer comprises Sr x Ti y O 3 in a perovskite material structure, wherein a concentration of Ti is greater than a concentration of Sr;
forming a dielectric layer comprising a perovskite material on the passivation layer; and
forming an upper electrode on the dielectric layer.

16. The method of claim 15 , wherein the forming of the passivation layer comprises:
exposing the lower electrode to the first gas for a first time;
sequentially exposing the lower electrode to the second gas for a second time and to the third gas for a third time, the sequentially exposing occurring after exposing the lower electrode to the first gas;
exposing the lower electrode to the fourth gas for a fourth time after exposing the lower electrode to the second gas and the third gas; and
exposing the lower electrode to the third gas for a fifth time after exposing the lower electrode to the fourth gas.

17. The method of claim 15 , wherein the second gas comprises at least one of water (H 2 O) and hydrogen peroxide (H 2 O 2 ).

18. The method of claim 15 , wherein the third gas comprises at least one of oxygen (O 2 ), ozone (O 3 ), and an oxygen radical (O).

19. The method of claim 16 , wherein the forming of the passivation layer comprises an atomic layer deposition (ALD) operation.

20. The method of claim 16 , wherein the lower electrode and the upper electrode each comprise one or more of SrVO 3 , SrMnO 3 , SrCrO 3 , SrFeO 3 , SrCoO 3 SrRuO 3 , SrMoO 3 , SrlrO 3 , SrNbO 3 , and SrCoO 3 .

Assignees

• Samsung Electronics Co Ltd
• Univ Ajou Ind Academic Coop Found

Inventors

• Lee Changsoo
• Lee Sangwoon
• Kim Yongsung
• Kim Jinhong
• Kim Hyungjun
• Lee Jooho

Classifications

• H10D1/692

  Electrodes · CPC title

• H01G4/1227

  based on alkaline earth titanates · CPC title

• H01G4/12

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

• H01G4/10

  Metal-oxide dielectrics {(H01G4/085 takes precedence)} · CPC title

• H10D1/696

  comprising multiple layers, e.g. comprising a barrier layer and a metal layer (barrier layers to prevent diffusion of hydrogen or oxygen in perovskite based capacitors H10D1/688) · CPC title