Multilevel wordline assembly for embedded DRAM

Patent metadata

Field	Value
Publication number	US-12446208-B2
Application number	US-202117358954-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Jun 25, 2021
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A device structure includes a first interconnect line along a longitudinal direction and a second interconnect line parallel to the first interconnect line, where the first interconnect structure is within a first metallization level and the second interconnect line is within a second metallization level. A first transistor and a laterally separated second transistor are on a same plane above the second interconnect line, where a gate of the first transistor is coupled to the first interconnect line and a gate of the second transistor is coupled to the second interconnect line. A first capacitor is coupled to a first terminal of the first transistor and a second capacitor is coupled to a first terminal of the second transistor. A third interconnect line couples a second terminal of the first transistor with a second terminal of the second transistor.

First claim

What is claimed is:

1. A device structure comprising:
a first interconnect line along a longitudinal direction, wherein the first interconnect line is within a first metallization level;
a second interconnect line parallel to the first interconnect line, wherein the second interconnect line is within a second metallization level;
a first transistor adjacent to a second transistor, the second transistor laterally separated from the first transistor, wherein a gate of the first transistor is coupled to the first interconnect line and wherein a gate of the second transistor is coupled to the second interconnect line;
a via between the first interconnect line and the gate of the first transistor;
a first capacitor and a second capacitor on a side of the first and second transistors opposite the first and second metallization levels, wherein the first capacitor is coupled to a first terminal of the first transistor and the second capacitor is coupled to a first terminal of the second transistor; and
a third interconnect line coupling a second terminal of the first transistor with a second terminal of the second transistor, the third interconnect line extending along a first direction orthogonal to the longitudinal direction,
wherein:
the via is a first via comprising a first end intersecting the first interconnect line and a second end intersecting the gate of the first transistor;
the device structure further comprises a second via comprising a first end intersecting the second interconnect line and a second end intersecting the gate of the second transistor;
the first interconnect line is separated from the second interconnect line by a first vertical thickness measured along a second direction orthogonal to the first and the longitudinal directions;
the second interconnect line has a second vertical thickness measured along the second direction;
the second via has a third vertical thickness measured along the second direction;
the first via has a fourth vertical thickness measured along the second direction and wherein the fourth vertical thickness is substantially equal to a sum of the first, the second and the third vertical thicknesses.

2. The device structure of claim 1 , wherein the second interconnect line is laterally separated from the first interconnect line by a first distance and the second transistor is laterally separated from the first transistor by a second distance.

3. The device structure of claim 2 , wherein the first distance is less than the second distance.

4. The device structure of claim 2 , wherein the first distance is zero.

5. The device structure of claim 1 , wherein the first interconnect line laterally overlaps the second interconnect line.

6. The device structure of claim 1 , wherein the first interconnect line and the second interconnect line each have a respective first lateral width as measured along a third direction orthogonal to the longitudinal direction, and wherein the first transistor and the second transistor each have a respective second lateral width as measured along the third direction and wherein the first lateral width is greater than the second lateral width.

7. The device structure of claim 1 , wherein a first terminal of the first capacitor is coupled to the first terminal of the first transistor and a first terminal of the second capacitor is coupled to the first terminal of the second transistor and wherein a second terminal of the first capacitor is coupled to a second terminal of the second capacitor.

8. A device structure comprising:
a first interconnect line along a longitudinal direction, wherein the first interconnect line is within a first metallization level;
a second interconnect line parallel to the first interconnect line, wherein the second interconnect line is within a second metallization level;
a first transistor adjacent to a second transistor, the second transistor laterally separated from the first transistor, wherein a gate of the first transistor is coupled to the first interconnect line and wherein a gate of the second transistor is coupled to the second interconnect line;
a via between the first interconnect line and the gate of the first transistor;
a first capacitor and a second capacitor on a side of the first and second transistors opposite the first and second metallization levels, wherein the first capacitor is coupled to a first terminal of the first transistor and the second capacitor is coupled to a first terminal of the second transistor; and
a third interconnect line coupling a second terminal of the first transistor with a second terminal of the second transistor, the third interconnect line extending along a first direction orthogonal to the longitudinal direction,
wherein the via is a first via and the device structure further comprises:
a third transistor and a fourth transistor on a same plane, the third transistor laterally separated from the fourth transistor, wherein a gate of the third transistor is coupled to the first interconnect line and wherein a gate of the fourth transistor is coupled to the second interconnect line;
a third via between the first interconnect line and the gate of the third transistor;
a third capacitor coupled to a first terminal of the third transistor and a fourth capacitor coupled to a first terminal of the fourth transistor; and
a fourth interconnect line coupling a second terminal of the third transistor with a second terminal of the fourth transistor, the second interconnect line extending along a direction orthogonal to the longitudinal direction.

9. The device structure of claim 8 , wherein the via is a first via and the device structure further comprises a second via coupled between the second interconnect line and the gate of the second transistor.

10. A method to fabricate a device structure, the method comprising:
forming a first interconnect line within a first metallization level, the first interconnect line extending along a first direction;
forming a second interconnect line within a second metallization level, wherein the second metallization level is above the first metallization level;
forming a first via on the first interconnect line and a second via on the second interconnect line, wherein the forming the first via and the second via comprises:
depositing a first etch stop layer on the first interconnect line;
depositing a dielectric on the first etch stop layer;
depositing a second etch stop layer on the dielectric;
etching a first opening in the second etch stop layer, in the dielectric and in the first etch stop layer;
depositing a first conductive material in the first opening on the first interconnect line;
removing excess first conductive material from a region outside of the first opening;
forming a second opening in the second etch stop layer;
depositing a second conductive material in the second opening on the second interconnect line; and
removing excess second conductive material from a region outside of the second opening;

forming a first transistor over the first via and electrically coupled to the first interconnect line through the first via;
forming a second transistor over the second via and electrically coupled to the second interconnect line through the second via;
forming a first capacitor over a plane of the first and second transistors and on a side of the transistors opposite the first and second interconnect lines, the first capacitor coupled to a first terminal of the first transistor;
forming a second capacitor over the plane of the first and second transistors and on a side of the transistors opposite the first and second interconnect lines, the second capacitor coupled to a first terminal of the second tra

Assignees

• Intel Corp

Inventors

• Alzate-Vinasco Juan G
• Lajoie Travis W
• Tan Elliot N
• Pierce Kimberly
• Ogadhoh Shem
• Sharma Abhishek A
• Sell Bernhard
• Wang Pei-Hua
• Ku Chieh-Jen

Classifications

• H10D30/6728

  Vertical TFTs · CPC title

• H10D30/031

  of thin-film transistors [TFT] · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/05

  Making the transistor · CPC title

• H10B12/488

  Word lines · CPC title