SRAM with P-type access transistors and complementary field-effect transistor technology

Patent metadata

Field	Value
Publication number	US-12446204-B2
Application number	US-202217686241-A
Country	US
Kind code	B2
Filing date	Mar 3, 2022
Priority date	Mar 3, 2022
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

Embodiments herein relate to scaling of Static Random Access Memory (SRAM) cells. An SRAM cell include nMOS transistors on one level above pMOS transistors on a lower level. Transistors on the two levels can have overlapping footprints to save space. Additionally, the SRAM cell can use pMOS access transistors in place of nMOS access transistors to allow reuse of areas of the cell which would otherwise be used by the nMOS access transistors. In one approach, gate interconnects are provided in these areas, which have an overlapping footprint with underlying pMOS access transistors to save space. The SRAM cells can be connected to bit lines and word lines in overhead and/or bottom metal layers. In another aspect, SRAM cells of a column are connected to bit lines in an overlying M 0 metal layer and an underlying BM 0 metal layers to reduce capacitance.

First claim

What is claimed is:

1. An apparatus, comprising:
a first n-type region comprising a first nMOS transistor and a first gate connector;
a second n-type region comprising a second nMOS transistor and a second gate connector;
a first p-type region below the first n-type region, the first p-type region comprising first and second pMOS transistors; and
a second p-type region below the second n-type region, the second p-type region comprising third and fourth pMOS transistors, wherein the first gate connector has an overlapping footprint with the first pMOS transistor.

2. The apparatus of claim 1 , wherein:
the first pMOS transistor is an access transistor coupled to a primary bit line and to a first node;
a control gate of the first pMOS transistor is coupled to a word line;
the fourth pMOS transistor is an access transistor coupled to a complementary bit line and to a second node;
a control gate of the fourth pMOS transistor is coupled to the word line;
the word line is in a M 0 metal layer above the first and second p-type regions; and
the primary bit line and the complementary bit line are in a M 2 metal layer above the M 0 layer.

3. The apparatus of claim 1 , wherein:
the first pMOS transistor is an access transistor coupled to a primary bit line and to a first node;
the fourth pMOS transistor is an access transistor coupled to a complementary bit line and to a second node;
the primary bit line and the complementary bit line are in respective portions of a BM 0 bottom metal layer shielded from one another by a respective portion of the BM 0 bottom metal layer to carry Vss; and
the BM 0 bottom metal layer is below the first and second p-type regions.

4. The apparatus of claim 1 , wherein:
the second gate connector has an overlapping footprint with the fourth pMOS transistor.

5. The apparatus of claim 1 , wherein:
the first pMOS transistor is an access transistor coupled to a primary bit line and to a first node;
the first gate connector is to connect a first portion of the first node to a second portion of the first node;
the first portion of the first node does not extend from the first n-type region to the second n-type region; and
the second portion of the first node extends from the first n-type region to the second n-type region.

6. The apparatus of claim 5 , wherein:
the fourth pMOS transistor is an access transistor coupled to a complementary bit line and to a second node;
the second gate connector is to connect a first portion of the second node to a second portion of the second node; and
the second portion of the second node extends from the first n-type region to the second n-type region.

7. The apparatus of claim 1 , wherein:
the second gate connector has an overlapping footprint with the fourth pMOS transistor; and
the fourth pMOS transistor is an access transistor coupled to a complementary bit line.

8. The apparatus of claim 1 , wherein:
the first n-type region has an overlapping footprint with the first p-type region; and
the second n-type region has an overlapping footprint with the second p-type region.

9. The apparatus of claim 1 , wherein:
the first nMOS transistor and the second pMOS transistor are in a first inverter and have coupled control gates; and
the second nMOS transistor and the third pMOS transistor are in a second inverter and have coupled control gates.

10. The apparatus of claim 1 , wherein the apparatus comprises a six- transistor static random access memory cell.

11. A static random access memory cell, comprising:
a first pMOS access transistor coupled to a primary bit line and to a first node;
a second pMOS access transistor coupled to a complementary bit line and to a second node N 1 ;
a first inverter coupled to the first and second nodes, the first inverter comprises a first nMOS transistor coupled to a first pMOS transistor;
a second inverter coupled to the first and second nodes, the second inverter comprises a second nMOS transistor coupled to a second pMOS transistor; and
a first gate connector to connect a first portion of the first node to a second portion of the first node, wherein the first gate connector is in a first n-type region, the first pMOS access transistor is in a first p-type region, and the first gate connector has an overlapping footprint with the first pMOS access transistor.

12. The static random access memory cell of claim 11 , further comprising:
a second gate connector to connect a first portion of the second node and to a second portion of the second node, wherein the second gate connector is in a second n-type region, the second pMOS access transistor is in a second p-type region, and the second gate connector has an overlapping footprint with the second pMOS access transistor.

13. The static random access memory cell of claim 12 , wherein:
the first n-type region overlays the first p-type region and has an overlapping footprint with the first p-type region; and
the second n-type region overlays the second p-type region and has an overlapping footprint with the second p-type region.

14. The static random access memory cell of claim 13 , wherein:
the first n-type region is separated from the second n-type region by an isolation region and the first p-type region is separated from the second p-type region by an isolation region.

15. The static random access memory cell of claim 12 , wherein:
the first gate connector is to connect a first portion of the first node to a second portion of the first node;
the first portion of the first node does not extend from the first n-type region to the second n-type region; and
the second portion of the first node extends from the first n-type region to the second n- type region.

16. An apparatus, comprising:
a first set of static random access memory (SRAM) cells;
a second set (of SRAM cells, the second set of SRAM cells are closer than the first set of SRAM cells to an associated sense amplifier;
a first primary bit line and a first complementary bit line in a first metal layer; and
a second primary bit line and a second complementary bit line in a second metal layer, wherein the first set of SRAM cells but not the second set of SRAM cells are coupled to the first primary bit line and the first complementary bit line in the first metal layer, and second set of SRAM cells but not the first set of SRAM cells are coupled to the second primary bit line and the second complementary bit line in the second metal layer.

17. The apparatus of claim 16 , wherein:
a number of SRAM cells in the second set of SRAM cells is at least twice a number of SRAM cells in the first set of SRAM cells.

18. The apparatus of claim 16 , wherein:
the first metal layer is an overlaying M 0 metal layer and the second metal layer is an underlying BM 0 bottom metal layer.

19. The apparatus of claim 16 , further comprising:
a first multiplexer having inputs coupled to the first primary bit line of the first metal layer and the second primary bit line in the second metal layer, and an output coupled to the sense amplifier; and
a second multiplexer having inputs coupled to the first complementary bit line of the first metal layer and the second complementary bit line in the second metal layer, and an output coupled to the sense amplifier.

20. The apparatus of claim 19 , wherein:
the first multiplexer and the second multiplexer are operable in response to a common select signal.

Assignees

• Intel Corp

Inventors

• Augustine Charles
• Subramaniam Seenivasan
• Morrow Patrick
• Khellah Muhammad M

Classifications

• G11C11/412

  using field-effect transistors only · CPC title

• G11C11/419

  Read-write [R-W] circuits · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H10D89/10

  Integrated device layouts · CPC title