On-chip shielded device

Patent metadata

Field	Value
Publication number	US-12446199-B2
Application number	US-202218048495-A
Country	US
Kind code	B2
Filing date	Oct 21, 2022
Priority date	Oct 21, 2022
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

One example discloses an on-chip shielded device, including: a planar structure including a substrate and a passivation layer; an electrical component formed within the substrate and coupled to an input signal path and an output signal path; a first shielding element positioned above the electrical component and the passivation layer; and a second shielding element positioned above the electrical component, the passivation layer and the first shielding element.

First claim

What is claimed is:

1. An on-chip shielded device, comprising:
a semiconductor material coupled to a passivation layer;
an electrical component formed within the semiconductor material and coupled to an input signal path and an output signal path;
a first shielding element positioned above the semiconductor material, the electrical component and the passivation layer; and
a second shielding element positioned above the semiconductor material, the electrical component, the passivation layer and the first shielding element;
wherein the first shielding element and the second shielding element each have a lateral dimension that only covers the semiconductor material.

2. The on-chip shielded device of claim 1 :
wherein the electrical component is in direct contact with the first shielding element.

3. The on-chip shielded device of claim 1 :
wherein the electrical component is separated from the first shielding element by the passivation layer.

4. The on-chip shielded device of claim 1 :
wherein the first shielding element is an organic core and/or photoresist-like material.

5. The on-chip shielded device of claim 1 :
wherein the first shielding element is ferromagnetic, non-conductive, and/or has a high dielectric constant.

6. The on-chip shielded device of claim 1 :
wherein the first shielding element is configured to provide electromagnetic shielding between the electrical component and a set of additional electrical components embedded within the semiconductor material.

7. The on-chip shielded device of claim 1 :
wherein the second shielding element is a metal.

8. The on-chip shielded device of claim 7 :
wherein the second shielding element is coupled to the semiconductor material and positioned around all sides of the first shielding element other than a side of the first shielding element facing the passivation layer.

9. The on-chip shielded device of claim 1 :
wherein the first shielding element and the second shielding element are configured to block electromagnetic energy from reaching the electrical component.

10. The on-chip shielded device of claim 1 :
further comprising a metallization layer positioned above a diffusion layer formed within the semiconductor material and below the passivation layer.

11. The on-chip shielded device of claim 10 :
wherein the metallization layer includes a reference plane.

12. The on-chip shielded device of claim 11 :
wherein the electrical component is coupled to the reference plane.

13. The on-chip shielded device of claim 11 :
wherein the passivation layer includes a set of vias; and
wherein the set of vias couple the reference plane to the first shielding element.

14. The on-chip shielded device of claim 11 :
wherein the passivation layer includes a set of vias; and
wherein the set of vias couple the reference plane to the second shielding element.

15. The on-chip shielded device of claim 11 :
wherein the passivation layer includes a set of vias; and
wherein the vias couple the reference plane to either or both the first shielding element and the second shielding element; and
wherein the vias are arranged as a via-fence surrounding the electrical component.

16. The on-chip shielded device of claim 11 :
wherein the passivation layer includes a set of vias;
wherein the set of vias couple both the first shielding element and the second shielding element to the reference plane; and
wherein the electrical component is coupled to the reference plane.

17. The on-chip shielded device of claim 1 :
further comprising an encapsulation layer; and
wherein the encapsulation layer covers the first and second shielding elements.

18. The on-chip shielded device of claim 1 :
wherein the electrical component is a first electrical component formed within the semiconductor material;
further comprising a second electrical component, also formed within the semiconductor material and a diffusion layer; and
wherein the first and second electrical components are separated by a distance within the semiconductor material.

19. The on-chip shielded device of claim 18 :
further comprising,
a third shielding element coupled to the semiconductor material and positioned above the second electrical component; and
a fourth shielding element coupled to the semiconductor material and positioned above the second electrical component and the third shielding element;

wherein the first and second shielding elements are separated from the third and fourth shielding elements by the distance.

20. The on-chip shielded device of claim 19 :
further comprising an encapsulation layer; and
wherein the encapsulation layer covers the first, second, third and fourth shielding elements.

21. The on-chip shielded device of claim 1 :
wherein the input signal path and the output signal path are configured to connect with a set of nodes outside of the first and second shielding elements.

22. The on-chip shielded device of claim 1 :
wherein the electrical component is at least one of: a monolithic microwave integrated circuits (MMICs), a waveguide, an RF device, an RF tuner, an RF amplifier, an RF detector, or an RF antenna.

23. The on-chip shielded device of claim 1 :
wherein the first shielding element and the second shielding element are coupled to the semiconductor material.

24. An on-chip shielded device, comprising:
a planar structure including a semiconductor substrate and a passivation layer;
an electrical component formed within the semiconductor substrate and coupled to an input signal path and an output signal path;
a first shielding element positioned above the electrical component and the passivation layer; and
a second shielding element positioned above the electrical component, the passivation layer and the first shielding element;
a metallization layer positioned above a diffusion layer and below the passivation layer;
wherein the metallization layer includes a reference plane;
wherein the passivation layer includes a set of vias;
wherein the set of vias couple the reference plane to the second shielding element; and
wherein the first shielding element and the second shielding element each have a lateral dimension that only covers the semiconductor substrate.

Assignees

• Nxp Bv

Inventors

• Freidl Philipp Franz
• Acar Mustafa
• Kamphuis Antonius Hendrikus Jozef
• Björk Erik Daniel
• Giannakidis Konstantinos
• Bergman Jan Willem
• Mandamparambil Rajesh
• Mattheijssen Paul

Classifications

• H10W42/20 Primary

  protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons · CPC title

• H10W42/287

  materials for magnetic shielding, e.g. ferromagnetic materials · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W20/423

  Shielding layers · CPC title

• H05K9/0088

  comprising a plurality of shielding layers; combining different shielding material structure · CPC title