Filter circuit, dimming system, and electronic apparatus

US12446129B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12446129-B2
Application numberUS-202418664456-A
CountryUS
Kind codeB2
Filing dateMay 15, 2024
Priority dateJul 21, 2023
Publication dateOct 14, 2025
Grant dateOct 14, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A filter circuit including a first common mode suppression module, a first differential mode suppression module, a first differential mode capacitor module, a second differential mode suppression module, a second common mode suppression module, a second differential mode capacitor module, a rectifier module, and a π-shaped filter module; the first differential mode suppression module is electrically connected with the first common mode suppression module and the second differential mode suppression module, the second common mode suppression module is electrically connected with the second differential mode suppression module and the rectifier module, and the rectifier module is electrically connected with the π-shaped filter module; the first differential mode capacitor module is connected between the first differential mode suppression module and the second differential mode suppression module, the second differential mode capacitor module is connected between the second common mode suppression module and the rectifier module.

First claim

Opening claim text (preview).

What is claimed is: 1. A filter circuit, comprising: a first common mode suppression module, a first differential mode suppression module, a first differential mode capacitor module, a second differential mode suppression module, a second common mode suppression module, a second differential mode capacitor module, a rectifier module, and a π-shaped filter module; wherein the first differential mode suppression module is electrically connected with the first common mode suppression module and the second differential mode suppression module, respectively, the second common mode suppression module is electrically connected with the second differential mode suppression module and the rectifier module, respectively, and the rectifier module is electrically connected with the π-shaped filter module; the first differential mode capacitor module is connected between the first differential mode suppression module and the second differential mode suppression module, the second differential mode capacitor module is connected between the second common mode suppression module and the rectifier module, the first common mode suppression module is configured for electrically connecting with an alternating current power supply through a thyristor dimmer, and the π-shaped filter module is configured for electrically connecting with a booster circuit; wherein the first common mode suppression module and the second common mode suppression module are configured for suppressing a common mode interference signal in an alternating current voltage signal provided by the alternating current power supply; the first differential mode suppression module, the second differential mode suppression module, the first differential mode capacitor module, and the second differential mode capacitor module are configured for suppressing a differential mode interference signal in the alternating current voltage signal; the rectifier module is configured for rectifying the alternating current voltage signal into a direct current voltage signal; the π-shaped filter module is configured for filtering the direct current voltage signal and transmitting a filtered direct current voltage signal to the booster circuit; and wherein a sum of a capacitance capacity of the first differential mode capacitor module and the second differential mode capacitor module is less than or equal to a preset value, and a sum of a capacitance capacity of the π-shaped filter module is greater than the sum of the capacitance capacity of the first differential mode capacitor module and the second differential mode capacitor module. 2. The filter circuit according to claim 1 , wherein the sum of the capacitance capacity of the π-shaped filter module is 2 to 3 times of the sum of the capacitance capacity of the first differential mode capacitor module and the second differential mode capacitor module. 3. The filter circuit according to claim 1 , wherein the first common mode suppression module comprises a first common mode choke; a first input terminal of the first common mode choke is configured for electrically connecting with a live line of the alternating current power supply through the thyristor dimmer; and a second input terminal of the first common mode choke is configured for electrically connecting with a neutral line of the alternating current power supply; wherein the first output terminal and the second output terminal of the first common mode choke are electrically connected with the first differential mode suppression module. 4. The filter circuit according to claim 2 , wherein the first common mode suppression module comprises a first common mode choke; a first input terminal of the first common mode choke is configured for electrically connecting with a live line of the alternating current power supply through the thyristor dimmer; and a second input terminal of the first common mode choke is configured for electrically connecting with a neutral line of the alternating current power supply; wherein the first output terminal and the second output terminal of the first common mode choke are electrically connected with the first differential mode suppression module. 5. The filter circuit according to claim 1 , wherein the first differential mode suppression module comprises a first differential mode choke, a first resistor, a third differential mode choke, and a third resistor; a first terminal of the first differential mode choke is electrically connected with a first terminal of the first resistor and the first common mode suppression module, respectively; a second terminal of the first differential mode choke is electrically connected with a second terminal of the first resistor, the first differential mode capacitor module, and the second differential mode suppression module, respectively; a first terminal of the third differential mode choke is electrically connected with a first terminal of the third resistor and the first common mode suppression module, respectively; and a second terminal of the third differential mode choke is electrically connected with a second terminal of the third resistor, the first differential mode capacitor module, and the second differential mode suppression module, respectively; wherein an inductance amount of the first differential mode choke is equal to that of the third differential mode choke. 6. The filter circuit according to claim 2 , wherein the first differential mode suppression module comprises a first differential mode choke, a first resistor, a third differential mode choke, and a third resistor; a first terminal of the first differential mode choke is electrically connected with a first terminal of the first resistor and the first common mode suppression module, respectively; a second terminal of the first differential mode choke is electrically connected with a second terminal of the first resistor, the first differential mode capacitor module, and the second differential mode suppression module, respectively; a first terminal of the third differential mode choke is electrically connected with a first terminal of the third resistor and the first common mode suppression module, respectively; and a second terminal of the third differential mode choke is electrically connected with a second terminal of the third resistor, the first differential mode capacitor module, and the second differential mode suppression module, respectively; wherein an inductance amount of the first differential mode choke is equal to that of the third differential mode choke. 7. The filter circuit according to claim 1 , wherein the second differential mode suppression module comprises a second differential mode choke, a fourth differential mode choke, a second resistor, and a fourth resistor; a first terminal of the second differential mode choke is electrically connected with a first terminal of the second resistor, the first differential mode capacitor module, and the first differential mode suppression module, respectively; a second terminal of the second differential mode choke is electrically connected with a second terminal of the second resistor and the second common mode suppression module, respectively; a first terminal of the fourth differential mode choke is electrically connected with a first terminal of the fourth resistor, the first differential mode capacitor module, and the first differential mode suppression module, respectively; and a second terminal of the fourth differential mode choke is electrically connected with a second terminal of the fourth resistor and the second common mode suppression module respectively; wherein an inductance amount of the second differential mode choke is equal to that of the fourth differential mode choke. 8. The filter c

Assignees

Inventors

Classifications

  • H05B45/10Primary

    Controlling the intensity of the light · CPC title

  • using boost topology · CPC title

  • H05B45/34Primary

    Voltage stabilisation; Maintaining constant voltage · CPC title

  • Driver circuits · CPC title

  • H05B45/36Primary

    Circuits for reducing or suppressing harmonics, ripples or electromagnetic interferences [EMI] · CPC title

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What does patent US12446129B2 cover?
A filter circuit including a first common mode suppression module, a first differential mode suppression module, a first differential mode capacitor module, a second differential mode suppression module, a second common mode suppression module, a second differential mode capacitor module, a rectifier module, and a π-shaped filter module; the first differential mode suppression module is electri…
Who is the assignee on this patent?
Shenzhen Sunricher Tech Co Ltd, Elemental Led Inc
What technology area does this patent fall under?
Primary CPC classification H05B45/10. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 14 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).