Technologies for performance monitoring and management with empty polling

Patent metadata

Field	Value
Publication number	US-12445365-B2
Application number	US-202217846947-A
Country	US
Kind code	B2
Filing date	Jun 22, 2022
Priority date	Apr 12, 2018
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

Technologies for performance monitoring include a computing device having multiple processor cores. The computing device performs a training workload with a processor core by continuously polling an empty input queue. The computing device determines empty polling thresholds based on the empty polling workload. The computing device performs a packet processing workload with one or more processor cores by continuously polling input queues associated with network traffic. The computing device compares a measured number of empty polls performed by the packet processing workload against the empty polling thresholds. The computing device configures power management of one or more processor cores in response to the comparison. The computing device may determine empty polling trends and compare the measured number of empty polls and the empty polling trends to the empty polling thresholds. Other embodiments are described and claimed.

First claim

The invention claimed is:

1. An apparatus comprising:
interface circuitry;
machine readable instructions; and
at least one processor circuit to be programmed by the machine readable instructions to:
poll an empty input queue to determine a first empty polling count of the empty input queue during a first time period;
operating on a separate input queue containing a first quantity of data during the first time period, the first empty polling count associated with a first load threshold of the at least one processor circuit;
poll the empty input queue to determine a second empty polling count of the empty input queue during a second time period;
operating on the separate input queue containing a second quantity of data during the second time period, the second empty polling count associated with a second load threshold of the at least one processor circuit, and the second quantity of data greater than the first quantity of data;
poll the empty input queue to determine a plurality of runtime empty polling counts of the empty input queue during a third time period while operating on the separate input queue with an unknown quantity of data;
determine an empty polling count trend based on the first load threshold, the second load threshold, and the plurality of runtime empty polling counts; and
cause a power state increase of the at least one processor circuit based on the trend moving toward the second load threshold; or
cause a power state decrease of the at least one processor circuit based on the trend moving toward the first load threshold.

2. The apparatus as defined in claim 1 , wherein one or more of the at least one processor circuit is to:
operate on the first quantity of data during the first time period to determine the first empty polling count based on a first quantity of empty polling values; and
operate on the second quantity of data during the second time period to determine the second empty polling count based on a second quantity of empty polling values.

3. The apparatus as defined in claim 2 , wherein one or more of the at least one processor circuit is to measure the first and second empty polling counts based on a series of ones of the empty polling values.

4. The apparatus as defined in claim 2 , wherein one or more of the at least one processor circuit is to determine if one of the first or second quantity of data includes packet data.

5. The apparatus as defined in claim 4 , wherein one or more of the at least one processor circuit is to increase a counter corresponding to the empty polling values when at least one of the first or second quantity of data does not include the packet data.

6. The apparatus as defined in claim 4 , wherein one or more of the at least one processor circuit is to cause at least one processing task to execute when at least one of the first or second quantity of data includes the packet data.

7. The apparatus as defined in claim 1 , wherein one or more of the at least one processor circuit is to cause the power state increase by at least one of activating a core, or increasing a frequency.

8. The apparatus as defined in claim 1 , wherein one or more of the at least one processor circuit is to cause the power state decrease by at least one of deactivating a core, or decreasing a frequency.

9. The apparatus as defined in claim 1 , wherein one or more of the at least one processor circuit is to cause at least one of the power state increase or the power state decrease for at least one of a central processing unit, a graphical processing unit, or a processor core.

10. The apparatus as defined in claim 1 , wherein one or more of the at least one processor circuit includes at least one of a central processing unit, a graphical processing unit, or a processor core.

11. At least one non-transitory computer-readable medium comprising computer-readable instructions to cause at least one processor circuit to at least:
poll an empty queue to determine a first empty polling count of the empty input queue during a first time period;
operate on a separate input queue containing a first quantity of data during the first time period, the first empty polling count associated with a first load threshold of the at least one processor circuit;
poll the empty input queue to determine a second empty polling count of the empty input queue during a second time period;
operate on the separate input queue containing a second quantity of data during the second time period, the second empty polling count associated with a second load threshold of the at least one processor circuit, and the second quantity of data greater than the first quantity of data;
poll the empty input queue to determine a plurality of runtime empty polling counts of the empty input queue during a third time period while operating on the separate input queue with an unknown quantity of data;
determine an empty polling count trend based on the first load threshold, the second load threshold, and the plurality of runtime empty polling counts; and
cause a power state increase of the at least one processor circuit based on the trend moving toward the second load threshold; or
cause a power state decrease of the at least one processor circuit based on the trend moving toward the first load threshold.

12. The at least one non-transitory computer-readable medium as defined in claim 11 , wherein the computer-readable instructions are to cause one or more of the at least one processor circuit to:
operate on the first quantity of data during the first time period to determine the first empty polling count based on a first quantity of empty polling values; and
process the second quantity of data during the second time period to determine the second empty polling count based on a second quantity of empty polling values.

13. The at least one non-transitory computer-readable medium as defined in claim 12 , wherein the computer-readable instructions are to cause one or more of the at least one processor circuit to increase the power state of the at least one processing circuit by at least one of activating a core, or increasing a frequency.

14. The at least one non-transitory computer-readable medium as defined in claim 12 , wherein the computer-readable instructions are to cause one or more of the at least one processor circuit to adjust the power state of at least one of a central processing unit, a graphical processing unit, or a processor core.

15. The at least one non-transitory computer-readable medium as defined in claim 12 , wherein the computer-readable instructions are to cause one or more of the at least one processor circuit to determine if one of the first or second quantity of data includes packet data.

16. The at least one non-transitory computer-readable medium as defined in claim 15 , wherein the computer-readable instructions are to cause one or more of the at least one processor circuit to one of (a) increase a counter corresponding to empty polling when the first or second quantity of data does not include the packet data or (b) cause processing tasks to execute when the first or second quantity of data includes the packet data.

17. A method comprising:
polling an empty input queue to determine, by executing an instruction with processing circuitry, a first empty polling count of the empty input queue during a first time period;
operating on a separate input queue containing a first quantity of data during the first time period, the first empty polling count associated with a first load threshold of the processing circuitry;
polling the empty input queue to d

Assignees

• Intel Corp

Inventors

• Mccarthy Peter
• Macnamara Chris
• Browne John
• Ma Liang J
• Day Liam

Classifications

• G06F1/3209

  Monitoring remote activity, e.g. over telephone lines or network connections · CPC title

• H04L43/16

  Threshold monitoring · CPC title

• H04L43/022

  by sampling · CPC title

• H04L41/0833

  for reduction of network energy consumption · CPC title

• H04L43/10 Primary

  Active monitoring, e.g. heartbeat, ping or trace-route · CPC title