Mitigating FPGA related risks

Patent metadata

Field	Value
Publication number	US-12445311-B2
Application number	US-202318505546-A
Country	US
Kind code	B2
Filing date	Nov 9, 2023
Priority date	May 9, 2021
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A host computer with a FPGA is communicatively coupled to a configuration computer via a communication network. The host computer receives target configuration data from the configuration computer in encrypted form. A scanner module that is associated with the host computer decrypts the target configuration data and scans it for malicious code. The module writes the target configuration data to the fabric area of the FPGA and thereby configures the FPGA accordingly, to enable execution of a target array application. The scanner module is associated with the host computer by being implemented as trusted execution environment, or as an on-array-processor.

First claim

The invention claimed is:

1. Computer-implemented method for operating a host computer that is communicatively coupled to a configuration computer via a communication network, and that is associated with a FPGA having a fabric area, the method being a method to configure the FPGA to execute a target array application, the method comprising:
the host computer forwarding identity information of the FPGA to the configuration computer, and the host computer receiving target configuration data from the configuration computer in encrypted form, wherein the encrypted form has been prepared by processing a response previously obtained by challenging the FPGA with a challenge;
receiving target configuration data ([TARGET_CONFIG]) from the configuration computer in encrypted form;
by a scanner module that is connected to the FPGA, decrypting the target configuration data and scanning the target configuration data for malicious code;
for malicious code being absent, writing the target configuration data to the fabric area of the FPGA, thereby configuring the FPGA accordingly, to enable execution of the target array application; and
confirming the integrity of the target array application on the FPGA by using the response in an auxiliary array application associated with the host computer, wherein the auxiliary array application causes the FPGA to transmit a proof value to the configuration computer.

2. Method according to claim 1 , wherein confirming the integrity of the target array application on the FPGA comprises the following steps:
the configuration computer 100 - 2 obtaining a nonce and communicating this to a previously installed auxiliary array application,
the configuration computer 100 - 2 calculating a first proof value,
the auxiliary array application using the response and the nonce to calculate a second proof value as well;
the auxiliary array application causing the FPGA to transmit the second proof value to the configuration computer;
the configuration computer comparing the first and the second proof values and confirms or denies the integrity.

3. Method according to claim 2 , wherein the host computer receives the target configuration data from the configuration computer in encrypted form prepared by processing the response by challenging the FPGA with a challenge response function.

4. Method according to claim 3 , wherein the challenge response function is selected from a physical unclonable function and a manufacturer-defined function.

5. Method according to claim 1 , wherein the scanner module is related to the FPGA by being implemented as an on-array-processor that is an element of a first part of the fabric area of the FPGA, and the scanner module writes the target configuration data to a second part of the fabric area by writing the target configuration data in decrypted form.

6. Method according to claim 5 , wherein the on-array-processor is a processor with a security extension.

7. Method according to claim 1 , wherein the scanner module is related to the FPGA through implementation by an FPGA associated computer that runs a trusted execution environment (TEE).

8. Method according to claim 7 , wherein the FPGA associated computer that implements the scanner module is selected from the following: the host computer, and a support computer that is associated with the host computer.

9. Method according to claim 7 , wherein, prior to writing the target configuration data to the fabric area of the FPGA, the following steps are performed:
obtaining auxiliary configuration data from the configuration computer in non-encrypted form;
authenticating the configuration computer by the FPGA generating a nonce value, sending the nonce value to the configuration computer, and receiving a proof value from the configuration computer made from the nonce value and from the challenge value, and upon successful authentication, configuring an auxiliary array application on the FPGA based on the auxiliary configuration data.

10. Method according to claim 9 , with the further step of checking the integrity of the auxiliary array application after the auxiliary array application has been configured.

11. Method according to claim 7 , wherein the configuration computer and the trusted execution environment (TEE) communicate the key to decrypt the target configuration data by a secure communication link implementing a key exchange procedure.

12. Method according to claim 7 , wherein the configuration computer and the trusted execution environment (TEE) communicate a target configuration key by processing a response that the configuration computer uses to calculate the target configuration key.

13. Method according to claim 12 , wherein the auxiliary array application on the FPGA decrypts the target configuration data by the target configuration key.

14. A computer program product for operating a host computer that is communicatively coupled to a configuration computer via a communication network, and that is associated with a FPGA having a fabric area, and for configuring the FPGA to execute a target array application, the computer program product being tangibly embodied on a non-transitory computer-readable storage medium and comprising instructions that, when executed by at least one computing device, are configured to cause the at least one computing device to:
forward identity information of the FPGA from the host computer to the configuration computer;
receive target configuration data from the configuration computer at the host computer in encrypted form, wherein the encrypted form has been prepared by processing a response previously obtained by challenging the FPGA with a challenge;
receive target configuration data ([TARGET_CONFIG]) from the configuration computer in encrypted form;
decrypt, by a scanner module that is connected to the FPGA, the target configuration data;
scan the target configuration data for malicious code;
for malicious code being absent, write the target configuration data to the fabric area of the FPGA, thereby configuring the FPGA accordingly, to enable execution of the target array application; and
confirm the integrity of target array application on the FPGA by using the response in an auxiliary array application associated with the host computer, wherein the auxiliary array application causes the FPGA to transmit a proof value to the configuration computer.

15. A system for operating a host computer that is communicatively coupled to a configuration computer via a communication network, and that is associated with a FPGA having a fabric area, and for configuring the FPGA to execute a target array application, the system comprising:
at least one memory including instructions;
and at least one processor that is operably coupled to the at least one memory and that is arranged and configured to execute instructions that, when executed, cause the at least one processor to:
forward identity information of the FPGA from the host computer to the configuration computer;
receive target configuration data at the host computer data the configuration computer in encrypted form, wherein the encrypted form has been prepared by processing a response previously obtained by challenging the FPGA with a challenge;
receive target configuration data ([TARGET_CONFIG]) from the configuration computer in encrypted form;
decrypt, by a scanner module that is connected to the FPGA, the target configuration data;
scan the target configuration data for malicious code;
for malicious code being absent, write the target configuration data to the fabric area of the FPGA, and thereby configuring the F

Assignees

• Univ Darmstadt Tech
• Koch Dirk
• Univ Leuven Kath
• Imec Vzw
• Dirk Koch
• imee vzw

Inventors

• Koch Dirk
• Sadeghi Ahmad-Reza
• Vliegen Jo
• Zeitouni Shaza
• Mentens Nele

Classifications

• G06F2221/034

  Test or assess a computer or a system · CPC title

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F21/51

  at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• G06F21/56

  Computer malware detection or handling, e.g. anti-virus arrangements · CPC title