Error correcting code encoding circuit and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-12445151-B2
Application number	US-202318520707-A
Country	US
Kind code	B2
Filing date	Nov 28, 2023
Priority date	Apr 6, 2023
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A semiconductor device may include an error correcting code (ECC) encoder that encodes a codeword based on a parity check matrix and generates the encoded codeword including an information bit and a parity bit. The parity check matrix is divided into an information part corresponding to the information bit and a parity part corresponding to the parity bit. The parity part includes a block matrix T including a plurality of first sub-matrices arranged in a dual diagonal structure, a block matrix B including a first sub-matrix and a (1−a)-th sub-matrix, a block matrix D composed of a first sub-matrix, and a block matrix E including a first sub-matrix and a masked (1−(a+1))-th sub-matrix. A location where the first sub-matrix is placed in the block matrix B precedes a location where the masked (1−(a+1))-th sub-matrix is placed in the block matrix E.

First claim

What is claimed is:

1. An error correcting code (ECC) encoding circuit configured to encode a codeword based on a parity check matrix and to generate an encoded codeword (ECW) including an information bit and a parity bit,
wherein the ECC encoding circuit includes:
a parity check matrix (PCM) generator configured to generate the parity check matrix; and
an encoding unit coupled to the PCM generator and configured to generate the encoded codeword based on the codeword and the parity check matrix;
wherein the parity check matrix is divided into an information part corresponding to the information bit and a parity part corresponding to the parity bit, and
wherein the parity part includes:
a block matrix T including a plurality of first sub-matrices arranged in a dual diagonal structure;
a block matrix B including a first sub-matrix and a (1−a)-th sub-matrix, a being a natural number greater than or equal to 1;
a block matrix D composed of the first sub-matrix; and
a block matrix E including the first sub-matrix and a masked (1−(a+1))-th sub-matrix,
wherein the block matrix B and the block matrix D are positioned in the same sub-column,
wherein the block matrix T and the block matrix E are positioned in the same sub-column,
wherein a location where the first sub-matrix is placed in the block matrix B precedes a location where the masked (1−(a+1))-th sub-matrix is placed in the block matrix E,
wherein a location where the (1−a)-th sub-matrix is placed in the block matrix B precedes a location where the first sub-matrix is placed in the block matrix E,
wherein the first sub-matrix of each of the block matrices T, B, D and E is defined as a unit matrix having a size of Z×Z, Z being a natural number,
wherein the (1−a)-th sub-matrix is defined as a matrix obtained by performing a left-cyclic shift ‘a’ times on the first sub-matrix, and
wherein the masked (1−(a+1))-th sub-matrix is defined as a matrix in which a first row is masked in a matrix obtained by performing a left-cyclic shift “a+1” times on the first sub-matrix.

2. The ECC encoding circuit of claim 1 ,
wherein a relationship between the parity check matrix and the encoded codeword is expressed based on Equation 1:

H
·
ECW

=

[

Hinfo

Hpar

]

[

s

p

]

=

Hinfo
·
s

+

Hpar
·
p

=
0

,

[

Equation
⁢

1

]

and
wherein, in Equation 1, the ‘H’ denotes the parity check matrix, the ECW denotes the encoded codeword, the Hinfo denotes the information part of the PCM, the Hpar denotes the parity part of the PCM, the ‘s’ denotes the information bit of the ECW, and the ‘p’ denotes the parity bit of the ECW.

3. The ECC encoding circuit of claim 2 , wherein the encoding unit is further configured to perform an operation for calculating the parity bit, and
wherein the operation for calculating the parity bit is expressed based on Equation 2:

p
=

Hpar

-
1

(

Hinfo
·
s

)

.

[

Equation
⁢

2

]

4. The ECC encoding circuit of claim 3 , wherein the parity bit includes a first parity bit operated with the block matrix B and the block matrix D and a second parity bit operated with the block matrix T and the block matrix E, and
wherein the encoding unit includes a computing unit configured to calculate the first parity bit.

5. The ECC encoding circuit of claim 2 , wherein the PCM generator includes:
a base matrix generator configured to generate a base matrix including a block matrix Bb, a block matrix Tb, a block matrix Db, and a block matrix Eb, which respectively correspond to the block matrix B, the block matrix T, the block matrix D, and the block matrix E of the parity part and each of which is composed of components of ‘1’ or ‘0’;
a mapping table configured to store mapping data including data for sub-matrices with which components respectively corresponding to the block matrix Bb, the block matrix Tb, the block matrix Db, and the block matrix Eb of the base matrix are to be replaced; and
a matrix transform unit configured to generate the parity check matrix including the parity part based on the base matrix and the mapping data.

6. The ECC encoding circuit of claim 5 , wherein a weight of a column divided into the block matrix Bb and the block matrix Db is 3, and
wherein a weight of at least one of columns divided into the block matrix Tb and the block matrix Eb is 3.

7. The ECC encoding circuit of claim 5 , wherein the block matrix Bb includes first and second components of ‘1’ and a plurality of components of ‘0’,
wherein the block matrix Eb includes first and second components of ‘1’ and a plurality of components of ‘0’,
wherein the block matrix Tb includes a plurality of components of ‘1’ arranged

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Kijun
• Park Kyoungbin
• Son Hong Rak
• Yang Dae-Yeol
• Yu Geunyeong
• Jun Bohwan
• Hwang Youngjun

Classifications

• H03M13/1168

  wherein the sub-matrices have column and row weights greater than one, e.g. multi-diagonal sub-matrices · CPC title

• H03M13/616 Primary

  Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations · CPC title

• H03M13/6502

  Reduction of hardware complexity or efficient processing · CPC title

• H03M13/611

  Specific encoding aspects, e.g. encoding by means of decoding · CPC title

• H03M13/118

  Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure (H03M13/1165 takes precedence) · CPC title