Channel circuit with asynchronous sampling from an oversampled analog-to-digital converter

Patent metadata

Field	Value
Publication number	US-12445142-B2
Application number	US-202318354138-A
Country	US
Kind code	B2
Filing date	Jul 18, 2023
Priority date	Sep 16, 2022
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

Example channel circuits, data storage devices, and methods for asynchronous sampling from an oversampled analog-to-digital converter are described. The channel circuit may include an analog-to-digital converter configured to generate an oversampled digital signal from an analog data signal using a sample rate that is an integer multiple of the baud rate of the channel circuit. A digital sample interpolator may then interpolate interpolated digital signal values from multiple signal values of the oversampled digital signal and select values at baud rate to generate a baud rate digital signal. The baud rate digital signal may be used by an iterative detector in a timing loop and, once a target timing is achieved, for the iterative detector to detect data bits from the interpolated digital signal.

First claim

What is claimed is:

1. A channel circuit, comprising:
an analog-to-digital converter configured with a sample rate that is an integer multiple of a baud rate of the channel circuit to generate an oversampled digital signal from an analog data signal;
a digital sample interpolator configured to:
receive the oversampled digital signal;
interpolate multiple digital sample values from the oversampled digital signal to determine interpolated digital signal values; and
output a baud rate digital signal comprised of interpolated digital signal values selected at the baud rate of the channel circuit; and

an iterative detector configured to detect data bits from the baud rate digital signal.

2. The channel circuit of claim 1 , wherein the analog-to-digital converter receives a time base signal of at least the sample rate.

3. The channel circuit of claim 1 , wherein the iterative detector is further configured to detect the data bits from the baud rate digital signal based on a target timing, wherein the target timing is based on alignment of the selected interpolated digital signal values with data bit representations from the analog data signal.

4. The channel circuit of claim 3 , further comprising:
an equalization circuit configured to:
equalize the baud rate digital signal from the analog-to-digital converter; and
provide the baud rate digital signal to the iterative detector.

5. The channel circuit of claim 4 , further comprising:
a gradient engine configured to:
determine a timing gradient from the iterative detector and the equalization circuit; and
feedback the timing gradient to the digital sample interpolator, wherein the digital sample interpolator, the iterative detector, the equalization circuit, and the gradient engine comprise a timing loop configured to align a timing of the baud rate digital signal with the target timing.

6. The channel circuit of claim 1 , further comprising:
a plurality of iterative detectors configured to detect data bits from a plurality of baud rate digital signals based on a target timing, wherein:
the digital sample interpolator is configured with a plurality of offset values for determining the plurality of baud rate digital signals;
the plurality of iterative detectors includes the iterative detector;
the plurality of baud rate signals includes the baud rate signal; and
the target timing is based on alignment of the selected interpolated digital signal values with data bit representations from the analog data signal.

7. The channel circuit of claim 6 , wherein the plurality of offset values comprises:
a zero offset value;
at least one positive offset value; and
at least one negative offset value.

8. The channel circuit of claim 1 , wherein the digital sample interpolator uses at least two-point polynomial interpolation based on a digital finite impulse response structure.

9. The channel circuit of claim 1 , wherein the sample rate of the analog-to-digital converter is at least double the baud rate of the channel circuit.

10. The channel circuit of claim 1 , further comprising:
an anti-aliasing filter configured to:
receive the oversampled digital signal from the analog-to-digital converter;
implement a stop-band for the oversampled digital signal; and
output the oversampled digital signal to the digital sample interpolator.

11. A data storage device comprising the channel circuit of claim 1 and further comprising:
a non-volatile storage medium configured to store data; and
a read element configured to generate the analog data signal from the non-volatile storage medium.

12. A method comprising:
generating, by an analog-to-digital converter configured with a sample rate that is an integer multiple of a baud rate of a channel circuit, an oversampled digital signal from an analog data signal;
interpolating, by a digital sample interpolator, multiple digital sample values from the oversampled digital signal to determine interpolated digital signal values; and
determining, by the digital sample interpolator and for use by an iterative detector, a baud rate digital signal comprised of interpolated digital signal values selected at the baud rate of the channel circuit.

13. The method of claim 12 , further comprising:
receiving, by the analog-to-digital converter, a time base signal of at least the sample rate.

14. The method of claim 12 , further comprising:
detecting, by the iterative detector, data bits from the baud rate digital signal based on a target timing, wherein the target timing is based on alignment of the selected interpolated digital signal values with data bit representations from the analog data signal.

15. The method of claim 14 , further comprising:
equalizing the baud rate digital signal from the analog-to-digital converter for use by the iterative detector.

16. The method of claim 14 , further comprising:
determining a timing gradient from the iterative detector;
feeding back the timing gradient to the digital sample interpolator; and
aligning a timing of the baud rate digital signal with the target timing.

17. The method of claim 12 , further comprising:
determining, by the digital sample interpolator and using a plurality of offset values, a plurality of baud rate digital signals from the oversampled digital signal;
providing the plurality of baud rate digital signals to a plurality of iterative detectors;
detecting, by the plurality of iterative detectors and from corresponding baud rate digital signals of the plurality of baud rate digital signals, data bits based on a target timing, wherein the target timing is based on alignment of the selected interpolated digital signal values with data bit representations from the analog data signal; and
selecting, based on a comparison of the detected data bits, the corresponding baud rate digital signal for use in decoding data from the analog data signal.

18. The method of claim 17 , wherein determining the plurality of baud rate digital signals includes:
determining, using a zero offset value, a first baud rate digital signal of the plurality of baud rate digital signals;
determining, using a positive offset value, a second baud rate digital signal of the plurality of baud rate digital signals; and
determining, using a negative offset value, a third baud rate digital signal of the plurality of baud rate digital signals.

19. The method of claim 12 , wherein interpolating interpolated digital signal values uses at least two-point polynomial interpolation based on a digital finite impulse response structure.

20. The method of claim 12 , wherein the sample rate of the analog-to-digital converter is at least double the baud rate of the channel circuit.

21. A data storage device comprising:
a non-volatile storage medium;
a channel circuit;
means for generating, using a sample rate that is an integer multiple of a baud rate of the channel circuit, an oversampled digital signal from an analog data signal;
means for interpolating multiple digital sample values from the oversampled digital signal to determine interpolated digital signal values;
means for determining a baud rate digital signal comprised of interpolated digital signal values selected at the baud rate of the channel circuit; and
means for determining timing for iterative detection of data bits from the baud rate digital signal based on a target timing, wherein the target timing is based on alignment of the selected interpolated digital signal values with data bit re

Assignees

• Western Digital Tech Inc

Inventors

• Galbraith Richard
• Ross Michael J
• Hanson Weldon M
• Contreras John T
• Oboukhov Iouri
• Ravindran Niranjay
• Bellam Pradhan
• Burton Derrick E

Classifications

• H03M1/0629

  Anti-aliasing · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• G11B5/09

  Digital recording · CPC title

• H03M1/207 Primary

  using a digital interpolation circuit · CPC title

• G11B20/10037 Primary

  A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof · CPC title