Power management circuit

US12444966B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12444966-B2
Application numberUS-202217895645-A
CountryUS
Kind codeB2
Filing dateAug 25, 2022
Priority dateDec 26, 2019
Publication dateOct 14, 2025
Grant dateOct 14, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of managing power and a power management circuit are presented. The power management circuit includes a three terminals switching converter coupled to a controller. The switching converter has a single inductor and two sets of switches. The first set of switches is coupled to an input terminal. The second set of switches is coupled to a battery terminal. The single inductor is provided between a first switching node and a second switching node. A controller is configured to generate a first error signal, and a second error signal and to provide the inductor current to the second terminal when the second error signal is greater than the first error signal or to the third terminal when the second error signal is less than the first error signal.

First claim

Opening claim text (preview).

What is claimed is: 1. A power management circuit comprising a switching converter coupled to a controller for operating the switching converter, the switching converter comprising a first set of switches coupled to a first terminal for receiving an input voltage; a second set of switches coupled to a second terminal for coupling to a battery; a single inductor, the single inductor being provided between a first switching node of the first set of switches and a second switching node of the second set of switches; and wherein the controller is configured to generate a first error signal, and a second error signal and to provide an inductor current of the single inductor to the second terminal when the second error signal is greater than the first error signal or to a third terminal when the second error signal is less than the first error signal. 2. The power management circuit of claim 1 , comprising a bypass switch coupled between the second terminal and the third terminal for coupling to a load; a transition switch provided between the first switching node and the second or the third terminal; and wherein the controller is configured to select a mode of operation by changing a state of at least one of the bypass switch and the transition switch. 3. The power management circuit of claim 2 , wherein the controller is configured to open the bypass switch and the transition switch to operate the switching converter as a single input dual output buck converter. 4. The power management circuit of claim 1 , wherein the controller is adapted to maintain a voltage at the third terminal at or above a predetermined value. 5. The power management circuit of claim 4 , wherein the first error signal is proportional to a difference between a sensed voltage at the third terminal and the predetermined value. 6. The power management circuit of claim 3 , wherein the controller is adapted to open the bypass switch and the transition switch to operate the switching converter as a single input dual output buck converter when the first error signal is between an intermediate voltage and a threshold voltage. 7. The power management circuit of claim 1 , wherein the first set of switches comprises a first switch coupled to a second switch at a first switching node; and wherein the second set of switches comprises a third switch coupled to a fourth switch at a second switching node. 8. The power management circuit of claim 7 , comprising a fifth switch coupled between the second switching node and the third terminal. 9. The power management circuit as claimed in claim 8 , wherein the controller is configured to operate the first, second, third, fourth and fifth switches to magnetize and demagnetize the single inductor to distribute energy from the first terminal either to the second terminal or to the third terminal. 10. The power management circuit of claim 1 , wherein the controller is adapted to generate the second error signal based on a difference between the voltage at the second terminal and a reference signal. 11. The power management circuit of claim 1 , wherein the controller comprises a battery charger controller adapted to generate the second error signal, a comparator adapted to compare the first and second error signals, a driver and a memory device. 12. The power management circuit of claim 11 , wherein the battery charger controller comprises a plurality of error amplifiers, each error amplifier being configured to provide a corresponding error signal. 13. The power management circuit of claim 11 , wherein the controller comprises a first PWM controller configured to receive the first error signal; a second PWM controller configured to receive the second error signal; and a multiplexer configured to receive the PWM signals of the first and second PWM controllers, respectively. 14. The power management circuit of claim 1 , comprising a current adjuster coupled to the second terminal, the current adjuster being adapted to control a current for charging the battery. 15. The power management circuit of 14 , wherein the current adjuster comprises a current mirror coupled to a reference circuit adapted to provide a reference battery voltage. 16. The power management circuit of claim 15 , wherein the current adjuster comprises a differential amplifier adapted to control the current flowing through the current mirror based on the reference battery voltage. 17. The power management circuit of claim 1 , wherein the controller is adapted to operate the switching converter in a buck-boost mode when a voltage is supplied to the first terminal. 18. A method of managing power comprising providing a switching converter comprising a first set of switches coupled to a first terminal for receiving an input voltage; a second set of switches coupled to a second terminal for coupling to a battery; a single inductor, the single inductor being provided between a first switching node of the first set of switches and a second switching node of the second set of switches; generating a first error signal, and a second error signal; and providing an inductor current of the single inductor to the second terminal when the second error signal is greater than the first error signal or to a third terminal when the second error signal is less than the first error signal. 19. The method as claimed in claim 18 , comprising providing a bypass switch coupled between the second terminal and the third terminal for coupling to a load; providing a transition switch provided between the first switching node and the second or the third terminal; and selecting a mode of operation by changing a state of at least one of the bypass switch and the transition switch. 20. The method as claimed in claim 19 , comprising operating the switching converter as a single input dual output buck converter by opening the bypass switch and the transition switch.

Assignees

Inventors

Classifications

  • H02J7/96Primary

    in response to battery voltage · CPC title

  • Battery or charger load switching, e.g. concurrent charging and load supply (H02J7/50 takes precedence) · CPC title

  • H02M3/1582Primary

    Buck-boost converters (H02M3/1584 takes precedence) · CPC title

  • for charging batteries from AC mains by converters · CPC title

  • Charging or discharging characterised by the power electronics converter · CPC title

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What does patent US12444966B2 cover?
A method of managing power and a power management circuit are presented. The power management circuit includes a three terminals switching converter coupled to a controller. The switching converter has a single inductor and two sets of switches. The first set of switches is coupled to an input terminal. The second set of switches is coupled to a battery terminal. The single inductor is provided…
Who is the assignee on this patent?
Dialog Semiconductor Uk Ltd, Renesas Design Uk Ltd
What technology area does this patent fall under?
Primary CPC classification H02J7/96. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 14 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).