Semiconductor memory device performing a multiplication and accumulation operation

Patent metadata

Field	Value
Publication number	US-12444467-B2
Application number	US-202218148333-A
Country	US
Kind code	B2
Filing date	Dec 29, 2022
Priority date	Jul 7, 2022
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A semiconductor memory device includes a cell array including a plurality of memory cells connected between a first bit line and a source line; a computation control circuit configured to control a first bit line current between the first bit line and the source line during a computation operation; and an output circuit including a first computation capacitor whose charge amount is changed according to the first bit line current during the computation operation, wherein an amount of charge that flows between the first bit line and the source line during the computation operation depends on both data stored in a memory cell among the plurality of memory cells according to a first data and a voltage of a word line connected to the memory cell provided according to a second data.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a cell array including a plurality of memory cells connected between a first bit line and a source line, the plurality of memory cells being connected to a plurality of word lines, respectively;
a computation control circuit configured to control a first bit line current between the first bit line and the source line to have a constant value during a computation operation; and
an output circuit including a first computation capacitor whose charge amount is changed according to the first bit line current during the computation operation,
wherein an amount of charge that flows between the first bit line and the source line during the computation operation depends on both data stored in a memory cell among the plurality of memory cells according to a first data and a voltage of a word line connected to the memory cell provided according to a second data,
wherein the computation operation includes a multiplication and accumulation (MAC) operation having a result corresponding to a sum of respective products of elements of the first data and elements of the second data,
wherein the MAC operation is performed by reading each of the plurality of memory cells storing a value corresponding to an element of the first data by providing a word line voltage determined according to a corresponding element of the second data and a read voltage which is selected from one or more threshold voltages used to determine values stored in corresponding memory cells, and
wherein a voltage of the first computation capacitor corresponds to a result of a MAC operation of the first data and the second data after the computation operation.

2. The semiconductor memory device of claim 1 , wherein the output circuit includes a switch configured to connect a first voltage source and the first computation capacitor according to a precharge signal; and a switch configured to connect the first bit line and the first computation capacitor according to a selection signal.

3. The semiconductor memory device of claim 2 , wherein the output circuit further includes an analog-to-digital converter (ADC) configured to convert a voltage of the first computation capacitor into a digital signal.

4. The semiconductor memory device of claim 2 , wherein the first computation capacitor is connected to the first bit line during the computation operation after the first computation capacitor is precharged.

5. The semiconductor memory device of claim 1 , further comprising a transistor configured to control the first bit line current according to a source line control signal,
wherein the transistor operates as a current mirror to produce the constant value of the first bit line current during the computation operation.

6. The semiconductor memory device of claim 1 , wherein the cell array includes a NAND string including a plurality of flash memory cells connected in series and a switch configured to connect a terminal of the NAND string with the first bit line according to a drain selection signal.

7. The semiconductor memory device of claim 6 , further comprising an input circuit configured to control word line voltage provided to each flash memory cell in the NAND string according to a respective element of the second data.

8. The semiconductor memory device of claim 1 ,
wherein the cell array includes:
a first NAND string connected between the first bit line and the source line, and
a second NAND string connected between a second bit line and the source line;
wherein the computation control circuit is configured to control a second bit line current between the second bit line and the source line to have a constant value during the computation operation;
wherein the output circuit includes a second computation capacitor whose charge amount is changed according to the second bit line current during the computation operation; and
wherein a result of the computation operation corresponds to a difference between a voltage of the first computation capacitor and a voltage of the second computation capacitor.

9. The semiconductor memory device of claim 8 , wherein the output circuit includes:
a switch configured to connect a first voltage source and the first computation capacitor;
a switch configured to connect the first bit line and the first computation capacitor;
a switch configured to connect the first voltage source and the second computation capacitor; and
a switch configured to connect the second bit line and the second computation capacitor.

10. The semiconductor memory device of claim 8 , wherein the first computation capacitor is connected to the first bit line during the computation operation after the first computation capacitor is precharged and the second computation capacitor is connected to the second bit line during the computation operation after the second computation capacitor is precharged.

11. The semiconductor memory device of claim 8 , further comprising:
a first transistor configured to connect the first NAND string to the source line and to operate as a current mirror to control the first bit line current during the computation operation, and
a second transistor configured to connect the second NAND string to the source line and to operate as a current mirror to control the second bit line current during the computation operation.

12. The semiconductor memory device of claim 8 ,
wherein each element of the first data is stored in a respective memory cell in the first NAND string and in a respective memory cell in the second NAND string;
wherein during the computation operation:
word lines coupled to the memory cells in the first NAND string are provided with one or more read voltages when a value of a corresponding element of second data corresponds to “1” and are not provided with the one or more read voltages when the value of the corresponding element of second data does not correspond to “1”, and
word lines coupled to the memory cells in the second NAND string are provided with one or more read voltages when a value of a corresponding element of second data corresponds to “−1” and are not provided with the one or more read voltages when the value of the corresponding element of second data does not correspond to “−1”.

Assignees

• Sk Hynix Inc
• Korea Advanced Inst Sci & Tech

Inventors

• Kim Kyunghyun
• Cho Seonghwan

Classifications

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G06N3/063

  using electronic means · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title