Display substrate, manufacturing method thereof and display apparatus

Patent metadata

Field	Value
Publication number	US-12444356-B2
Application number	US-202218267788-A
Country	US
Kind code	B2
Filing date	Jul 29, 2022
Priority date	Jul 29, 2022
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A display substrate, a manufacturing method thereof and a display apparatus are provided. The display substrate includes multiple sub-pixels, a sub-pixel includes a first region (q1), a gap region (q3) and a second region (q2); the sub-pixel includes a first transistor (T1) including first active layer (1) and first gate electrode (11), a second transistor (T2) including second active layer (2) and second gate electrode (12) and a third transistor (T3) including third active layer (3) and third gate electrode (13); the first active layer is disposed in the first region, the second active layer and the third active layer are disposed in the second region, and via holes through which the first gate electrode and the third gate electrode are connected to a scan signal line and a via hole through which the second gate electrode is connected to the first transistor are provided in the gap region.

First claim

The invention claimed is:

1. A display substrate, comprising a display area and a border area,
wherein the display area comprises a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns,
a sub-pixel comprises a first region, a gap region and a second region arranged in sequence along a pixel row direction;
at least one sub-pixel comprises a pixel driving circuit, a first scan signal line and a second scan signal line,
the pixel driving circuit at least comprises a first transistor, a second transistor and a third transistor,
the first scan signal line is configured to control turning-on or turning-off of the first transistor, and the second scan signal line is configured to control turning-on or turning-off of the second transistor;
the first transistor at least comprises a first gate electrode, a first active layer, a first electrode and a second electrode of the first transistor, the second transistor at least comprises a second gate electrode and a second active layer, and the third transistor at least comprises a third gate electrode and a third active layer;
the first active layer is disposed in the first region, the second active layer and the third active layer are disposed in the second region, and the second active layer is disposed in a plane at one side of the third active layer in a pixel column direction;
the first scan signal line is connected to the first gate electrode through a first gate via hole, the second electrode of the first transistor is connected to the second gate electrode through a second gate via hole, the second scan signal line is connected to the third gate electrode through a third gate via hole, and the first gate via hole, the second gate via hole and the third gate via hole are provided in the gap region.

2. The display substrate according to claim 1 , wherein long the pixel row direction, the first region has a first width, the second region has a second width, and the gap region has a third width, the third width is less than or equal to 0.5*the first width, and the third width is less than or equal to 0.5*the second width.

3. The display substrate according to claim 1 , wherein first gate electrodes of two adjacent sub-pixels in a pixel row are connected to each other to form an integrated structure, and third gate electrodes of two adjacent sub-pixels in a pixel row are connected to each other to form an integrated structure.

4. The display substrate according to claim 3 , wherein the first gate electrodes of the integrated structure are connected to the first scan signal line through two first gate via holes, and the third gate electrodes of the integrated structure are connected to the second scan signal line through two third gate via holes.

5. The display substrate according to claim 1 , wherein first transistors, second transistors and third transistors of two adjacent sub-pixels in a pixel row are mirror symmetrical with respect to a pixel centerline, which is a straight line located between the two adjacent sub-pixels in the pixel row and extending along the pixel column direction.

6. The display substrate according to claim 1 , wherein in at least one sub-pixel, the first gate electrode comprises a first gate body portion and a first gate connection portion connected to each other, the first gate connection portion is disposed in the gap region, and the first scan signal line is connected to the first gate connection portion through the first gate via hole;
or
in at least one sub-pixel, the second gate electrode comprises a second gate body portion and a second gate connection portion connected to each other, the second gate connection portion is disposed in the gap region, and the second electrode of the first transistor is connected to the second gate connection portion through the second gate via hole;
or
in at least one sub-pixel, the third gate electrode comprises a third gate body portion and a third gate connection portion connected to each other, the third gate connection portion is disposed in the gap region, and the second scan signal line is connected to the third gate connection portion through the third gate via hole.

7. The display substrate according to claim 1 , wherein in at least one sub-pixel, the first gate electrode comprises a first gate body portion and a first gate connection portion connected to each other, the first gate connection portion is disposed at one side of the first gate body portion close to the third gate electrode, and the third gate electrode comprises a third gate body portion and a third gate connection portion connected to each other, the third gate connection portion is disposed at one side of the third gate body portion close to the first gate electrode, and the first gate connection portion and the third gate connection portion are interlaced in the pixel column direction.

8. The display substrate according to claim 7 , wherein an edge of the first gate body portion and an edge of the first gate connection portion that are away from the second transistor are flush, and an edge of the third gate body portion and an edge of the third gate connection portion that are close to the second transistor are flush.

9. The display substrate according to claim 1 , wherein in at least one sub-pixel, the second gate electrode comprises a second gate body portion and a second gate connection portion connected to each other, the second gate connection portion is disposed in the gap region, and an edge of the second gate body portion and an edge of the second gate connection portion that are close to the third transistor are flush.

10. The display substrate according to claim 1 , wherein a main part of the first scan signal line and a main part of the second scan signal line are in a shape of a line extending along the pixel row direction, an orthographic projection of the first scan signal line on a plane of the display substrate at least partially overlaps with orthographic projections of the first gate electrode and the third gate electrode on the plane of the display substrate, and an orthographic projection of the second scan signal line on the plane of the display substrate at least partially overlaps with the orthographic projections of the first gate electrode and the third gate electrode on the plane of the display substrate.

11. The display substrate according to claim 1 , wherein the second transistor further comprises a first electrode and a second electrode of the second transistor, and the third transistor further comprises a first electrode and a second electrode of the second transistor, the first electrode of the first transistor is connected to a data signal line, the first electrode of the second transistor is connected to a light emitting voltage line, the first electrode of the third transistor is connected to a reference signal line, and the second electrode of the second transistor and the second electrode of the third transistor are connected to each other to form an integrated structure.

12. The display substrate according to claim 1 , wherein in at least one sub-pixel, the pixel driving circuit further comprises a storage capacitor comprising a first plate and a second plate, an orthographic projection of the first plate on a plane of the display substrate at least partially overlaps with an orthographic projection of the second plate on the plane of the display substrate, the first plate is connected to the second electrode of the first transistor through a connection electrode, and the second plate is connected to a first power supply line.

13. The display substrate according to claim 1 , wherein at least one sub-pixel fu

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Cong Ning
• Fan Longfei
• Li Dachao
• Zhang Can
• Xuan Minghua
• Chen Xiaochuan

Classifications

• H10K59/1315

  comprising structures specially adapted for lowering the resistance · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/1201

  Manufacture or treatment · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title