Queue-pair management

Patent metadata

Field	Value
Publication number	US-12443547-B2
Application number	US-202318229075-A
Country	US
Kind code	B2
Filing date	Aug 1, 2023
Priority date	Aug 1, 2023
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A system is described which monitors accesses to one or more peers using queue pairs (QPs). Each access is associated with a respective peer of the one or more peers. The system identifies, based on one or more of a rate and a count of the monitored accesses to the one or more QPs, a first peer of the one or more peers. In response to identifying the first peer, a reliable connection QP is established for the first peer of the one or more peers.

First claim

What is claimed is:

1. A system comprising one or more circuits to:
monitor accesses to one or more peers using dynamically connected (DC) queue pairs (QPs), wherein each access is associated with a respective peer of the one or more peers;
identify, based on one or more of a rate and a count of the monitored accesses to the one or more DC QPs, a first peer of the one or more peers; and
in response to identifying the first peer, store a pointer to a reliable connection (RC) QP for the first peer of the one or more peers in a memory of a central processing unit (CPU) and establish the RC QP for the first peer.

2. The system of claim 1 , wherein monitoring the accesses comprises reading a counter associated with the first peer.

3. The system of claim 2 , wherein the counter is stored in a memory of a graphics processing unit (GPU), and the one or more circuits comprise one or more of the CPU and a network interface controller (NIC).

4. The system of claim 3 , wherein the counter is accessed by the CPU using loads and stores.

5. The system of claim 2 , wherein the counter is a first array including a field for each of the one or more peers, and wherein the one or more circuits update a second array with instructions based on values in the first array.

6. The system of claim 2 , wherein the counter is one of a plurality of counters, and wherein each counter is associated with a respective peer of the one or more peers.

7. The system of claim 2 , wherein the rate is a rate of an increase in the counter over a period of time.

8. The system of claim 2 , wherein identifying the first peer comprises determining the counter associated with the first peer is greater than a counter associated with a second peer.

9. The system of claim 1 , wherein the one or more circuits comprise one or more of the CPU and a graphics processing unit (GPU), and wherein the access to the one or more peers is performed by the one or more of the CPU and the GPU.

10. The system of claim 9 , wherein establishing the RC QP comprises creating a send queue and a receive queue in memory, and wherein one or more of the CPU and the GPU communicates with the first peer by writing a work request to the send queue.

11. The system of claim 1 , wherein the one or more circuits are further to:
monitor accesses to one or more RC QPs;
identify, based on one or more of a rate and a count of the monitored accesses to the RC QPs, a first RC QP of the one or more RC QPs, wherein the first RC QP is associated with a second peer of the one or more peers; and
in response to identifying the first RC QP, terminate the first RC QP.

12. The system of claim 11 , wherein, after terminating the first RC QP, communication with the second peer associated with the first RC QP is conducted using a DC QP.

13. The system of claim 11 , wherein terminating the first RC QP is further in response to determining a number of available slots for RC QPs.

14. The system of claim 1 , wherein the one or more circuits are further to determine a rank of each of the one or more peers based on the one or more of the rate and the count of the monitored accesses.

15. The system of claim 14 , wherein the one or more circuits are further to establish an RC QP for one or more of the one or more peers based on the rank.

16. The system of claim 1 , wherein establishing the RC QP comprises determining a slot number for the RC QP and writing the slot number to a memory device.

17. A system comprising one or more circuits to:
increase a first counter associated with a first peer of a plurality of peers with each access to the first peer via one or more dynamically connected (DC) queue pairs (QPs), wherein the first counter is one of a plurality of counters, wherein each counter is associated with a respective peer of the plurality of peers;
receive a reliable connection (RC) slot number associated with the first peer; and
in response to receiving the RC slot number, initiate an RC QP with the first peer.

18. The system of claim 17 , wherein the one or more circuits are further to:
receive an indication to terminate the RC QP with the first peer; and
in response to the indication to terminate the RC QP with the first peer, communicate with the first peer via one of the one or more DC QPs.

19. A networking device, comprising:
a first one or more circuits to:
communicate with two or more peers via one or more dynamically connected (DC) queue pairs (QPs); and
increase, for each access to the DC QPs, one of a plurality of counters, wherein each counter is associated with a respective one of the two or more peers; and

a second one or more circuits to:
monitor a value of each of the counters;
identify, based on one or more of a rate and a count of the monitored value of each of the counters, a first peer of the two or more peers; and
in response to identifying the first peer, establish a reliable connection (RC) QP for the first peer of the one or more peers.

20. The networking device of claim 19 , wherein the rate is a rate of an increase in one or more of the counters over a period of time.

Assignees

• Mellanox Technologies Ltd

Inventors

• Markthub Pak
• Dinan James
• Potluri Sreeram
• Genkin Leonid
• Itigin Yossef
• Hasson Shahar Refael

Classifications

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F15/163 Primary

  Interprocessor communication · CPC title