Cache systems

Patent metadata

Field	Value
Publication number	US-12443538-B2
Application number	US-202218067180-A
Country	US
Kind code	B2
Filing date	Dec 16, 2022
Priority date	Dec 21, 2021
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A method of operating a cache system is disclosed. Information indicating a link between associated header and payload cache entries is maintained. The link information may be used to reduce cache coherency traffic.

First claim

What is claimed is:

1. A method of operating a cache system that comprises plural coherent caches operable to cache data stored in memory for a processor;
the method comprising:
maintaining link information indicating, for a cache entry in a cache of the plural coherent caches that caches payload data that is associated with header data that is cached by another cache entry in the same cache, a link between the cache entry in the cache that caches the payload data and the another cache entry in the same cache that caches the header data; and
maintaining cache coherence for the plural coherent caches using the link information by, in response to invalidation of a cache entry in the cache that caches header data:
using the link information to identify any cache entries in the same cache that cache payload data that is associated with the header data; and
invalidating the identified cache entries.

2. The method of claim 1 , wherein the link information comprises one or more pointers, each pointer pointing from a cache entry in the cache to another cache entry in the same cache.

3. The method of claim 1 , comprising:
maintaining coherency information that indicates what header data is cached by the plural coherent caches;
maintaining cache coherence for the plural coherent caches in respect of header data using the coherency information; and
maintaining cache coherence for the plural coherent caches in respect of payload data using the link information.

4. The method of claim 1 , comprising invalidating the cache entry that caches the header data when evicting the cache entry that caches the header data from the cache, or in response to a request to invalidate the cache entry that caches the header data.

5. The method of claim 1 , wherein invalidating a cache entry in the cache that caches payload data comprises marking the cache entry as requiring invalidation, and then invalidating the marked cache entry.

6. The method of claim 1 , wherein the cache system further comprises a higher level cache operable to cache payload data in compressed form, and the plural coherent caches are lower level caches operable to cache payload data cached by the higher level cache in decompressed form.

7. The method of claim 1 , wherein payload data and associated header data comprise data for the same compression block.

8. The method of claim 1 , wherein the processor is a graphics processing unit.

9. A non-transitory computer readable storage medium storing software code which when executing on a processor performs a method as claimed in claim 1 .

10. A method of operating a cache system that comprises plural coherent caches operable to cache data stored in memory for a processor;
the method comprising:
maintaining link information indicating, for a cache entry in a cache of the plural coherent caches that caches payload data that is associated with header data that is cached by another cache entry in the same cache, a link between the cache entry in the cache that caches the payload data and the another cache entry in the same cache that caches the header data;
maintaining coherency information that indicates what header data is cached by the plural coherent caches;
maintaining cache coherence for the plural coherent caches in respect of header data using the coherency information; and
maintaining cache coherence for the plural coherent caches in respect of payload data using the link information.

11. A cache system comprising:
plural coherent caches operable to cache data stored in memory for a processor; and
a link maintaining circuit configured to maintain link information indicating, for a cache entry in a cache of the plural coherent caches that caches payload data that is associated with header data that is cached by another cache entry in the same cache, a link between the cache entry in the cache that caches the payload data and the another cache entry in the same cache that caches the header data;
wherein the cache system is configured to maintain cache coherence for the plural coherent caches using link information maintained by the link maintaining circuit by, in response to invalidation of a cache entry in the cache that caches header data:
using the link information to identify any cache entries in the same cache that cache payload data that is associated with the header data; and
invalidating the identified cache entries.

12. The system of claim 11 , wherein the link information comprises one or more pointers, each pointer pointing from a cache entry in the cache to another cache entry in the same cache.

13. The system of claim 11 , wherein the cache system is configured to:
maintain coherency information that indicates what header data is cached by the plural coherent caches;
maintain cache coherence for the plural coherent caches in respect of header data using the coherency information; and
maintain cache coherence for the plural coherent caches in respect of payload data using the link information.

14. The system of claim 11 , wherein the cache system is configured to invalidate the cache entry that caches the header data when evicting the cache entry that caches the header data from the cache, or in response to a request to invalidate the cache entry that caches the header data.

15. The system of claim 11 , wherein the cache system is configured to invalidate a cache entry in the cache that caches payload data by marking the cache entry as requiring invalidation, and then invalidating the marked cache entry.

16. The system of claim 11 , wherein the cache system further comprises a higher level cache operable to cache payload data in compressed form, and the plural coherent caches are lower level caches operable to cache payload data cached by the higher level cache in decompressed form.

17. The system of claim 11 , wherein payload data and associated header data comprise data for the same compression block.

18. A data processor comprising the cache system of claim 11 .

19. The system or processor of claim 11 , wherein the processor is a graphics processing unit.

20. A cache system comprising:
plural coherent caches operable to cache data stored in memory for a processor; and
a link maintaining circuit configured to maintain link information indicating, for a cache entry in a cache of the plural coherent caches that caches payload data that is associated with header data that is cached by another cache entry in the same cache, a link between the cache entry in the cache that caches the payload data and the another cache entry in the same cache that caches the header data;
wherein the cache system is configured to:
maintain coherency information that indicates what header data is cached by the plural coherent caches;
maintain cache coherence for the plural coherent caches in respect of header data using the coherency information; and
maintain cache coherence for the plural coherent caches in respect of payload data using link information maintained by the link maintaining circuit.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Uhrenholt Olof Henrik
• Fielding Edvard
• Jahren Ole Henrik

Classifications

• G06F12/0808

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/0815 Primary

  Cache consistency protocols · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F12/0824

  Distributed directories, e.g. linked lists of caches · CPC title