Conditional modular subtraction instruction

Patent metadata

Field	Value
Publication number	US-12443409-B2
Application number	US-202117476726-A
Country	US
Kind code	B2
Filing date	Sep 16, 2021
Priority date	Sep 16, 2021
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

One embodiment provides a processor comprising first circuitry to decode an instruction into a decoded instruction, the instruction to indicate a first source operand and a second source operand and second circuitry including a processing resource to execute the decoded instruction, wherein responsive to the decoded instruction, the processing resource is to output a result of first source operand data minus second source operand data in response to a determination by the processing resource that the first source operand data is greater than or equal to the second source operand data, otherwise the processing resource is to output the first source operand data.

First claim

What is claimed is:

1. A processor comprising:
first circuitry to decode an instruction, the instruction to indicate a first source packed data operand and a second source packed data operand, the first source packed data operand to have a first plurality of integer data elements and the second source packed data operand to have a second plurality of integer data elements; and
second circuitry including a processing resource to perform operations corresponding to the instruction, including to:
determine whether each integer data element of the first plurality of integer data elements of the first source packed data operand is greater than or equal to a corresponding integer data element of the second plurality of integer data elements of the second source packed data operand;
for each integer data element of the first plurality of integer data elements that is greater than or equal to the corresponding integer data element of the second plurality of integer data elements, output a corresponding result data element in a result packed data that is equal to the integer data element of the first plurality of integer data elements minus the corresponding integer data element of the second plurality of integer data elements; and
for each integer data element of the first plurality of integer data elements that is not greater than or equal to the corresponding integer data element of the second plurality of integer data elements, output the corresponding integer data element of the first plurality of integer data elements as a corresponding result data element in the result packed data.

2. The processor as in claim 1 , wherein the first plurality of integer data elements and the second plurality of integer data elements are 32-bit integer data elements.

3. The processor as in claim 1 , wherein the first plurality of integer data elements and the second plurality of integer data elements are 64-bit integer data elements.

4. The processor as in claim 1 , wherein the instruction is to indicate a destination operand to specify a destination and the processing resource is to store the result packed data to the destination.

5. The processor as in claim 4 , further comprising a register file having a plurality of registers of differing widths, wherein the destination operand is to specify a first register within the register file and the first source packed data operand or the second source packed data operand are to be stored in a second register within the register file.

6. The processor as in claim 5 , wherein the destination operand is to specify a 128-bit register, a 256-bit register, or a 512-bit register.

7. An apparatus comprising:
decoder circuitry to decode an instruction, the instruction to include a field for an identifier of a first source packed data operand having a first plurality of integer data elements, a field for an identifier of a second source packed data operand having a second plurality of integer data elements, and a field for an opcode, the opcode to indicate execution circuitry is to perform a conditional subtraction operations on the first source packed data operand and the second source packed data operand; and
the execution circuitry to perform the conditional subtraction operations according to the opcode, including to perform the conditional subtraction operations in parallel on each integer data element of the first plurality of integer data elements and corresponding integer data elements of the second plurality of integer data elements, the execution circuitry including:
a first circuit to generate subtraction results based on integer data element of the first plurality of integer data elements minus corresponding integer data elements of the second plurality of integer data elements and status flags to indicate signs of the subtraction results; and
a second circuit to output the integer data elements of the first plurality of integer data elements when the status flags indicate that the subtraction results are negative and otherwise to output the subtraction results.

8. The apparatus as in claim 7 , wherein the field for the identifier of the first source packed data operand or the second source operand is to identify a vector register.

9. The apparatus as in claim 7 , wherein the field for the identifier of the first source packed data operand is to identify a memory location.

10. The apparatus as in claim 7 , wherein the integer data elements of the first source packed data operand and the integer data elements of the second source packed data operand are 32-bit integer data elements.

11. The apparatus as in claim 7 , wherein the integer data elements of the first source packed data operand and the integer data elements of the second source packed data operand are 64-bit integer data elements.

12. The apparatus as in claim 7 , wherein the instruction is to indicate a destination to store the output integer data elements and the output subtraction results and destination includes a 128-bit, 256-bit, or 512-bit register.

13. A processor comprising:
first circuitry to decode an instruction, the instruction to indicate a first source packed data operand and a second source operand, the first source packed data operand to have a first plurality of integer data elements and the second source operand to have an integer data element; and
second circuitry including a processing resource to perform operations corresponding to the instruction, including to:
determine whether each integer data element of the first plurality of integer data elements is greater than or equal to the integer data element of the second source operand;
for each integer data element of the first plurality of integer data elements that is greater than or equal to the integer data element of the second source operand, output a corresponding result data element in a result packed data that is equal to the integer data element of the first plurality of integer data elements minus the integer data element of the second source operand; and
for each integer data element of the first plurality of integer data elements that is not greater than or equal to the integer data element of the second source operand, output the corresponding integer data element of the first plurality of integer data elements as a corresponding result data element in the result packed data.

14. The processor as in claim 13 , wherein the first plurality of integer data elements and the second plurality of integer data elements are either 32-bit integer data elements or 64-bit integer data elements.

15. The processor as in claim 13 , further comprising a register file having a plurality of registers of differing widths, wherein the destination operand is to specify a first register within the register file and the first source packed data operand or the second source packed data operand are to be stored in a second register within the register file.

Assignees

• Intel Corp

Inventors

• Boemer Fabian
• Gopal Vinodh
• Seifu Gelila
• Kim Sejun
• Crawford Jack

Classifications

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/30038

  using a mask · CPC title

• H04L9/30

  Public key, i.e. encryption algorithm being computationally infeasible to invert or user's encryption keys not requiring secrecy · CPC title

• H04L9/008

  involving homomorphic encryption · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title