Array substrate and method for manufacturing same, display panel, and display device

Patent metadata

Field	Value
Publication number	US-12443081-B2
Application number	US-202218686877-A
Country	US
Kind code	B2
Filing date	Oct 27, 2022
Priority date	Oct 27, 2022
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

Provided is an array substrate, including a substrate. The substrate includes a display region and a peripheral region surrounding the display region. The display region includes a plurality of pixel regions arranged in arrays. The array substrate further includes a plurality of GOA units and a plurality of gate lines. The plurality of GOA units are arranged along a first direction. The peripheral region includes a data pad (DP) region and a data pad opposite (DPO) region that are arranged opposite to each other along a second direction on two sides of the display region. The plurality of GOA units are within the DPO region, the plurality of gate lines are within the display region, and the plurality of GOA units are electrically connected to the plurality of gate lines. The first direction is intersected with the second direction.

First claim

What is claimed is:

1. An array substrate, comprising a substrate; wherein
the substrate comprises a display region and a peripheral region surrounding the display region, the display region comprising a plurality of pixel regions arranged in arrays;
the array substrate further comprises a plurality of GOA units and a plurality of gate lines, wherein the plurality of GOA units are arranged along a first direction, the peripheral region comprises a data pad (DP) region and a data pad opposite (DPO) region that are arranged opposite to each other along a second direction on two sides of the display region, the plurality of GOA units are within the DPO region, the plurality of gate lines are within the display region, and the plurality of GOA units are electrically connected to the plurality of gate lines, the first direction being intersected with the second direction; and
in the display region, the array substrate further comprises a gate layer, a gate insulator layer, a source-drain layer, a protection layer, and a common electrode layer that are successively stacked on the substrate, the common electrode layer comprising a gate connection line,
wherein the plurality of gate lines comprise a plurality of first gate lines and a plurality of second gate lines, wherein extension directions of the plurality of first gate lines are consistent with the second direction, extension directions of the plurality of second gate lines are consistent with the first direction, and the plurality of second gate lines are connected to the plurality of GOA units respectively by the plurality of first gate lines; and
the plurality of first gate lines are disposed in the source-drain layer, the plurality of second gate lines are disposed in the gate layer, the plurality of first gate lines are connected to the gate connection line through a first via in the protection layer, and the plurality of second gate lines are connected to the gate connection line through a second via in the gate insulator layer and the protection layer.

2. The array substrate according to claim 1 , wherein a number of the pixel regions in one row arranged along the first direction is greater than a number of the pixel regions in one column arranged along the second direction.

3. The array substrate according to claim 2 , wherein the plurality of the first gate lines are within a middle section of the display region.

4. The array substrate according to claim 3 , wherein one of the first gate lines is arranged in each column of the pixel regions in the middle section of the display region.

5. The array substrate according to claim 4 , wherein the pixel region comprises a first sub-region, a second sub-region, and a third sub-region that are arranged along the first direction, wherein the first sub-region is a green sub-region, and the first gate line is between the second sub-region and the third sub-region, or the first gate line is within the second sub-region or the third sub-region.

6. The array substrate according to claim 1 , wherein
the peripheral region further comprises a connection region between the display region and the DPO region; and
the array substrate further comprises a plurality of connection lines in the connection region, the plurality of first gate lines being connected to the plurality of GOA units respectively by the plurality of connection lines.

7. The array substrate according to claim 6 , wherein at least a portion of the connection lines are straight lines.

8. The array substrate according to claim 6 , wherein in the connection region, the array substrate further comprises a gate layer, a gate insulator layer, and a source-drain layer that are successively stacked on the substrate, and the plurality of connection lines comprise a plurality of first connection lines and a plurality of second connection lines;
wherein
the plurality of first connection lines are disposed in the source-drain layer, the plurality of first connection lines are directly connected to an output terminal of the GOA unit at a position, proximal to the DPO region, of the connection region, and the plurality of first connection lines are directly connected to the plurality of first gate lines at a position, proximal to the display region, of the connection region; and
the plurality of second connection lines are disposed in the gate layer, the plurality of second connection lines are connected to the output terminal of the GOA unit through a via at the position, proximal to the DPO region, of the connection region, and the plurality of second connection lines are connected to the plurality of first gate lines through a via at the position, proximal to the display region, of the connection region.

9. The array substrate according to claim 6 , wherein
in the connection region, the array substrate further comprises a gate layer, a gate insulator layer, and a source-drain layer that are successively stacked on the substrate; and
the plurality of connection lines are disposed in the source-drain layer, the plurality of connection lines are directly connected to an output terminal of the GOA unit at a position, proximal to the DPO region, of the connection region, and the plurality of connection lines are directly connected to the plurality of first gate lines at a position, proximal to the display region, of the connection region.

10. The array substrate according to claim 6 , wherein
in the connection region, the array substrate further comprises a gate layer disposed on the substrate; and
the plurality of connection lines are disposed in the gate layer, the plurality of connection lines are connected to an output terminal of the GOA unit through a via at a position, proximal to the DPO region, of the connection region, and the plurality of connection lines are connected to the plurality of first gate lines through a via at a position, proximal to the display region, of the connection region.

11. The array substrate according to claim 1 , wherein a number of the pixel regions in one row arranged along the first direction is greater than or equal to twice a number of the pixel regions in one column arranged along the second direction, a number of the first gate lines is equal to twice a number of the second gate lines, a number of the GOA units is greater than or equal to twice the number of the pixel regions in one column, each of the second gate lines is connected to two GOA units by two first gate lines, and the two GOA units connected to the same second gate line are arranged symmetrically with respect to a centerline, the centerline being a centerline of the substrate extending along the second direction.

12. The array substrate according to claim 1 , wherein boundaries of adjacent GOA units in the plurality of GOA units are coincident, and the GOA units disposed at two ends are respectively disposed on or near two sides of the display region in the first direction.

13. A display panel, comprising: an array substrate;
wherein the array substrate comprises a substrate; wherein
the substrate comprises a display region and a peripheral region surrounding the display region, the display region comprising a plurality of pixel regions arranged in arrays;
the array substrate further comprises a plurality of GOA units and a plurality of gate lines, wherein the plurality of GOA units are arranged along a first direction, the peripheral region comprises a data pad (DP) region and a data pad opposite (DPO) region that are arranged opposite to each other along a second direction on two sides of the display region, the plurality of GOA units are within the DPO region, the plurality of gate lines are within the d

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Zhang Yadong
• Li Ting
• Wu Bo
• Zuo Xiongcan

Classifications

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G3/3674

  Details of drivers for scan electrodes · CPC title

• G02F1/1368 Primary

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title