Pipelined histogram pixel

Patent metadata

Field	Value
Publication number	US-12442902-B2
Application number	US-202117143570-A
Country	US
Kind code	B2
Filing date	Jan 7, 2021
Priority date	Jan 9, 2020
Publication date	Oct 14, 2025
Grant date	Oct 14, 2025

Abstract

A Light Detection and Ranging (LIDAR) detector circuit includes a memory device comprising a first memory and a second memory, and at least one control circuit. The at least one control circuit is configured to execute first memory storage operations to store data indicated by detection signals received from one or more photodetector elements in the first memory during a first portion of a time between pulses of an emitter signal output from a LIDAR emitter element, and to execute second memory storage operations to include the data, which was stored in the first memory, in the second memory during a second portion of the time between the pulses of the emitter signal. Related devices and methods of operation are also discussed.

First claim

The invention claimed is:

1. A Light Detection and Ranging (LIDAR) detector circuit, comprising:
a non-transitory memory device comprising a first memory and a second memory; and
at least one control circuit configured to execute first memory storage operations to store data indicated by detection signals received from one or more photodetector elements in the first memory during a first portion of a time between pulses of an emitter signal output from a LIDAR emitter element, and to execute second memory storage operations to include the data, which was stored in the first memory, in the second memory during a second portion of the time between the pulses of the emitter signal,
wherein the first portion of the time comprises a strobe window of activation of the one or more photodetector elements, wherein the detection signals are output from the one or more photodetector elements in response to a plurality of photons incident thereon during the strobe window,
wherein the second portion of the time comprises a remainder of the time between the pulses of the emitter signal, after the strobe window and before a next pulse of the pulses of the emitter signal, and
wherein the first memory is a buffer memory device and the second memory is a main memory device, and wherein the at least one control circuit is further configured to execute the second memory storage operations to transfer the data from the buffer memory to be included in the main memory after the strobe window and before the next pulse of the emitter signal.

2. The LIDAR detector circuit of claim 1 , wherein the at least one control circuit comprises a sampler circuit that is configured to execute the first memory storage operations, and wherein the first memory storage operations comprise sampling the data from the detection signals at a predetermined sampling rate and writing the data to respective bins of the first memory.

3. The LIDAR detector circuit of claim 2 , wherein the at least one control circuit further comprises a memory controller that is configured to execute the second memory storage operations, and wherein the second memory storage operations comprise retrieving the data from the respective bins of the first memory and integrating the data into respective bins of the second memory, wherein the respective bins of the second memory comprise histogram data for an imaging distance subrange corresponding to the strobe window.

4. The LIDAR detector circuit of claim 3 , wherein the memory controller and the second memory are inactive during the first portion of the time, and wherein the sampler circuit is inactive during the second portion of the time.

5. The LIDAR detector circuit of claim 4 , wherein the second memory comprises static random access memory (SRAM) or a dynamic random access memory (DRAM), and wherein the second memory storage operations comprise precharge and read operations to retrieve the data from the respective bins of the first memory, and precharge, read, modify, and write operations to integrate the data into the respective bins of the second memory.

6. The LIDAR detector circuit of claim 1 , further comprising:
a detector interface circuit coupled to the at least one control circuit and configured to receive the detection signals from the one or more photodetector elements during the first portion of the time, wherein the detector interface circuit is inactive during the second portion of the time.

7. The LIDAR detector circuit of claim 1 , wherein:
the one or more photodetector elements comprise a subset of a plurality of photodetector elements, and respective subsets of the plurality of photodetector elements define respective detector pixels; and
the at least one control circuit comprises a shared control circuit that is configured to execute the first memory storage operations for the respective detector pixels during the first portion of the time, and is configured to execute the second memory storage operations for the respective detector pixels during the second portion of the time.

8. The LIDAR detector circuit of claim 7 , wherein the second memory comprises respective main memory devices, and wherein the shared control circuit is configured to execute the second memory storage operations to store respective data for the respective detector pixels in the respective main memory devices sequentially during the second portion of the time.

9. The LIDAR detector circuit of claim 7 , wherein the first memory comprises respective buffer memory devices, and wherein the shared control circuit is configured to execute the first memory storage operations to store respective data for the respective detector pixels in the respective buffer memory devices in parallel during the first portion of the time.

10. The LIDAR detector circuit of claim 1 , wherein the at least one control circuit is configured to execute the first memory storage operations responsive to a first clock signal, and to execute the second memory storage operations responsive to a second clock signal different than the first clock signal.

11. The LIDAR detector circuit of claim 1 , wherein the one or more photodetector elements comprise single-photon avalanche detectors (SPADs), and wherein the data comprises photon counts indicated by the detection signals corresponding to an imaging distance subrange defined by the strobe window.

12. A Light Detection and Ranging (LIDAR) detector circuit, comprising:
one or more photodetector elements defining a LIDAR detector pixel;
a buffer memory device;
a main memory device; and
at least one processor circuit configured to execute first and second memory storage operations to store data indicated by detection signals received from the LIDAR detector pixel in the buffer and main memory devices during first and second portions of a time between pulses of a LIDAR emitter signal, respectively,
wherein the first portion of the time comprises a strobe window of activation of the LIDAR detector pixel, and the second portion of the time comprises a remainder of the time between the pulses of the LIDAR emitter signal, after the strobe window and before a next pulse of the pulses of the LIDAR emitter signal, and
wherein data is transferred from the buffer memory to the main memory after a strobe window of activation of the one or more photodetector elements and before the next pulse of the emitter signal.

13. The LIDAR detector circuit of claim 12 , wherein the at least one processor circuit comprises:
a sampler circuit that is configured to execute the first memory storage operations to sample the data from the detection signals at a predetermined sampling rate and write the data to respective bins of the buffer memory device; and
a memory controller that is configured to execute the second memory storage operations to retrieve the data from the respective bins of the buffer memory device and integrate the data in respective bins of the main memory device, wherein the respective bins of the main memory device comprise histogram data for an imaging distance subrange corresponding to the strobe window.

14. The LIDAR detector circuit of claim 13 , wherein the memory controller and the main memory are inactive during the first portion of the time, and wherein the sampler circuit is inactive during the second portion of the time.

15. The LIDAR detector circuit of claim 14 , wherein:
the one or more photodetector elements define a respective LIDAR detector pixel of a plurality of LIDAR detector pixels, each of the LIDAR detector pixels being associated with a respective buffer memory device and a respective main memory device;

Assignees

• Sense Photonics Inc

Inventors

• Henderson Robert
• Al Abbas Tarek
• Storrar David

Classifications

• G01S17/931

  of land vehicles · CPC title

• G01S17/894 Primary

  Three-dimensional [3D] imaging with simultaneous measurement of time-of-flight at a two-dimensional [2D] array of receiver pixels, e.g. time-of-flight cameras or flash lidar · CPC title

• G01S7/4815

  using multiple transmitters · CPC title

• G01S7/4816

  of receivers alone · CPC title

• G01S17/10

  using transmission of interrupted, pulse-modulated waves (determination of distance by phase measurements G01S17/32) · CPC title