Display substrate and manufacturing method therefor, and display device

Patent metadata

Field	Value
Publication number	US-12439792-B2
Application number	US-202218245134-A
Country	US
Kind code	B2
Filing date	Mar 25, 2022
Priority date	Mar 25, 2022
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A display substrate and a manufacturing method therefor, and a display device. The display substrate includes: a base substrate including a special-shaped display area and a frame area located on one side of the special-shaped display area; and the special-shaped display area includes a first display area and a second display area on located on one side of the first display area, and the second display area is arranged in contact with the frame area; a group of data lines located on the base substrate and located in the first display area and the second display area; a group of fan-out lines located on a side of a layer where the group of data lines are located away from the base substrate, located in the first display area, and electrically connected to the data lines; and a group of dummy leads.

First claim

What is claimed is:

1. A display substrate, comprising:
a base substrate comprising a special-shaped display area and a frame area located on at least one side of the special-shaped display area; wherein the special-shaped display area comprises a first display area and a second display area located on at least one side of the first display area, and the second display area is arranged in contact with the frame area;
a data line located on the base substrate and located in the first display area and the second display area;
a plurality of fan-out lines located on a side of a layer where the data line is located away from the base substrate, and located in the first display area, wherein at least one of the plurality of fan-out lines is electrically connected to the data line; and
a plurality of dummy leads arranged in a same layer as the plurality of fan-out lines and located in the second display area, wherein a ratio of a distribution density of the plurality of dummy leads in the second display area to a distribution density of the plurality of fan-out lines in the first display area satisfies a preset threshold.

2. The display substrate according to claim 1 , wherein the preset threshold is greater than or equal to 0.5 and less than or equal to 1.5.

3. The display substrate according to claim 2 , wherein the preset threshold is greater than or equal to 0.8 and less than or equal to 1.2.

4. The display substrate according to claim 3 , wherein the preset threshold is 1.

5. The display substrate according to claim 1 , further comprising: a first power line located in the frame area and electrically connected to the plurality of dummy leads.

6. The display substrate according to claim 5 , wherein the first power line and the plurality of dummy leads form a closed loop;
wherein the display substrate further comprises: a connection line arranged in a same layer as the plurality of dummy leads, wherein the plurality of dummy leads form a closed loop with the first power line through the connection line.

7. The display substrate according to claim 5 , wherein the first power line is located at least in a layer where the plurality of dummy leads are located, and the first power line is integral with the plurality of dummy leads.

8. The display substrate according to claim 1 , further comprising a gate drive circuit located in the special-shaped display area.

9. The display substrate according to claim 8 , wherein the gate drive circuit comprises a plurality of shift registers arranged in cascade, and the plurality of shift registers are symmetrically arranged about a center axis of the special-shaped display area in a column direction.

10. The display substrate according to claim 9 , further comprising a plurality of sub-pixels arranged in an array in the special-shaped display area; wherein the plurality of shift registers are arranged in cascade at row gaps of rows of the sub-pixels along the column direction.

11. The display substrate according to claim 8 , further comprising a plurality of gate drive signal lines located in the first display area and the second display area and configured to provide control signals to the gate drive circuit.

12. The display substrate according to claim 11 , wherein the plurality of fan-out lines comprise fan-out line segments with a substantially same extending direction as the data line, and an extending direction of the plurality of gate drive signal lines is substantially same as an extending direction of the data line; and
orthographic projections of the fan-out line segments on the base substrate do not overlap with orthographic projections of the plurality of gate drive signal lines on the base substrate.

13. The display substrate according to claim 12 , wherein an extending direction of the plurality of dummy leads is substantially same as the extension direction of the data line; and
orthographic projections of the plurality of dummy leads on the base substrate do not overlap with the orthographic projections of the plurality of gate drive signal lines on the base substrate.

14. The display substrate according to claim 13 , further comprising a plurality of sub-pixels arranged in an array in the special-shaped display area, wherein each column of the sub-pixels comprises an edge area adjacent to a column gap;
the gate drive signal lines are located at some column gaps of columns of the sub-pixels;
in the first display area, the orthographic projections of the fan-out line segments on the base substrate at least partially overlap with orthographic projections of edge areas on the base substrate, and the orthographic projections of the fan-out line segments on the base substrate at least partially overlap with orthographic projections of other column gaps than the some column gaps on the base substrate; and
in the second display area, the orthographic projections of the plurality of dummy leads on the base substrate at least partially overlap with the orthographic projections of the edge areas on the base substrate, and the orthographic projections of the plurality of dummy leads on the base substrate at least partially overlap with the orthographic projections of other column gaps than the some column gaps on the base substrate.

15. The display substrate according to claim 13 , wherein in the first display area, the orthographic projections of the fan-out line segments on the base substrate are substantially evenly distributed among the orthographic projections of the gate drive signal lines on the base substrate; and
in the second display area, the orthographic projections of the dummy leads on the base substrate are substantially evenly distributed among the orthographic projections of the gate drive signal lines on the base substrate.

16. The display substrate according to claim 11 , wherein the plurality of fan-out lines comprise fan-out line segments with a substantially same extending direction as the data line, an extending direction of the plurality of dummy leads is substantially same as an extending direction of the data line, and an extending direction of the plurality of gate drive signal lines is substantially same as the extending direction of the data line; and
orthographic projections of the fan-out line segments on the base substrate and/or orthographic projections of the plurality of dummy leads on the base substrate at least partially overlap with orthographic projections of the plurality of gate drive signal lines on the base substrate.

17. The display substrate according to claim 16 , wherein the orthographic projections of the fan-out line segments on the base substrate and the orthographic projections of the plurality of dummy leads on the base substrate do not overlap with an orthographic projection of the data line on the base substrate respectively.

18. The display substrate according to claim 11 , further comprising a plurality of sub-pixels arranged in an array in the special-shaped display area, wherein every two adjacent columns of sub-pixels form a group, each column of sub-pixels are electrically connected to one data line, two data lines corresponding to each group of sub-pixels are located at a column gap between two columns of sub-pixels in the group; the plurality of gate drive signal lines are arranged in a same layer as the data line, and the gate drive signal lines are located at group gaps arranged at intervals among groups of sub-pixels;
wherein a shape of the special-shaped display area is a pattern, a letter, a digit or a Chinese character.

19. A man

Assignees

• Hefei Boe Joint Tech Co Ltd
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Wu Liu
• Yuan Zhidong
• Li Yongqian
• Yuan Can
• Chang Chuanchuan
• Liu Jun
• Sun Tao

Classifications

• H10K59/88

  Dummy elements, i.e. elements having non-functional features · CPC title

• H10K59/1201 Primary

  Manufacture or treatment · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/1315 Primary

  comprising structures specially adapted for lowering the resistance · CPC title