Display panel and display device

Patent metadata

Field	Value
Publication number	US-12439776-B2
Application number	US-202318221420-A
Country	US
Kind code	B2
Filing date	Jul 13, 2023
Priority date	Apr 26, 2018
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A display panel and a display device are provided. The display panel has a display area. The display panel includes: a base substrate; a driving circuit and at least one signal line on the base substrate; and at least one insulating layer between the driving circuit and the at least one signal line. The driving circuit is disposed in a periphery of the display area; and an orthogonal projection of at least one of the signal lines on the base substrate has an overlapping area with an orthogonal projection of the driving circuit on the base substrate.

First claim

What is claimed is:

1. A display panel, comprising:
a display area and a base substrate;
a driving circuit disposed on the base substrate, and comprising a plurality of transistors;
at least one signal line on the base substrate; and
at least one insulating layer between the driving circuit and the at least one signal line, wherein an orthogonal projection of the at least one signal line on the base substrate has an overlapping area with an orthogonal projection of the driving circuit on the base substrate;
wherein the at least one signal line is at least one electrode power supply line, and the at least one electrode power supply line comprises at least one first opening, and an area of an orthogonal projection of each opening of the at least one first opening on the base substrate, is larger than an area of an orthogonal projection of a group of transistors among the plurality of transistors on the base substrate, the group of transistors comprises at least two transistors, and an overlapping area, between an orthogonal projection of an non-opening area of the at least one electrode power supply line on the base substrate and an orthogonal projection of any transistor on the base substrate, is zero;
wherein the driving circuit comprises a plurality of metal traces;
the at least one electrode power supply line further comprises at least one second opening, and when the at least one second opening comprises a plurality of openings, one or more openings among the plurality of openings correspond to a same metal trace; and wherein
an overlapping area, of orthographic projections of the one or more openings on the base substrate and an orthographic projection of the same metal trace on the base substrate, is a first area, an area of the orthographic projection of the same metal trace on the base substrate is a second area, and the first area is at least 20% of the second area.

2. The display panel according to claim 1 , wherein:
the plurality of transistors comprise a driving transistor and a selection transistor; and
the at least one electrode power supply line further comprises at least one third opening, and the at least one third opening comprises two openings, one opening of the at least one third opening corresponding to the driving transistor and another one opening of the at least one third opening corresponding to the selection transistor.

3. The display panel according to claim 1 , wherein:
the display panel further comprises a plurality of light emitting devices disposed in the display area;
a first electrode of each of the plurality of light emitting devices is coupled to the at least one electrode power supply line; and
the first electrode is an electrode of the light emitting device away from the base substrate.

4. The display panel according to claim 3 , wherein the first electrodes of the plurality of light emitting devices are connected to each other to form an electrode layer, and the at least one electrode power supply line is coupled to the electrode layer.

5. The display panel according to claim 1 , wherein the first area is 80% or 90% of the second area.

6. The display panel according to claim 3 , wherein the driving circuit, the at least one insulating layer, and the at least one electrode power supply line are sequentially stacked on the base substrate.

7. The display panel according to claim 3 , wherein the at least one insulating layer comprises: at least one of an organic insulating layer or an inorganic insulating layer.

8. The display panel according to claim 7 , wherein:
the at least one insulating layer comprises: one organic insulating layer and one inorganic insulating layer, and
the inorganic insulating layer is disposed adjacent to the driving circuit, and the organic insulating layer is disposed adjacent to the at least one signal line.

9. The display panel according to claim 8 , wherein the organic insulating layer has a thickness larger than a thickness of the inorganic insulating layer.

10. The display panel according to claim 1 , wherein the base substrate is a flexible substrate.

11. The display panel according to claim 1 , wherein:
the driving circuit comprises an active layer, a gate electrode layer, and a source/drain electrode layer;
the at least one insulating layer is between the source/drain electrode layer and the at least one signal line; and
the at least one signal line is on the source/drain electrode layer and a material of the at least one signal line is same as a material of the source/drain electrode layer.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Tian Hongwei
• Niu Yanan
• Liu Zheng
• Li Liangjian
• Li Dong
• Zhao Meng
• Han Long
• Zheng Can

Classifications

• H10D86/451

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/411

  characterised by materials, geometry or structure of the substrates · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title