Array substrate and display apparatus comprising oxidization protective layer on copper conductive layer

Patent metadata

Field	Value
Publication number	US-12439691-B2
Application number	US-202117786177-A
Country	US
Kind code	B2
Filing date	Aug 26, 2021
Priority date	Aug 26, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

Embodiments of the present disclosure provide an array substrate and a display apparatus. The array substrate includes: a base substrate; a conductive layer located on the base substrate, where a material of the conductive layer includes copper; and an oxidization protective layer, located on a side, facing away from the base substrate, of the conductive layer; where a material of the oxidization protective layer includes tungsten.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate;
a conductive layer, arranged on the base substrate, wherein a material of the conductive layer comprises copper; and
an oxidization protective layer, arranged on a side, facing away from the base substrate, of the conductive layer; wherein a material of the oxidization protective layer comprises tungsten;
wherein the base substrate comprises a functional region; the functional region comprises a plurality of first pads arranged on the base substrate; the plurality of first pads are bonded with a plurality of light-emitting units; the conductive layer comprises an first region and a second region; and the first region in the conductive layer is the plurality of first pads;
wherein the base substrate further comprises a bonding region; the bonding region comprises a plurality of second pads arranged on the base substrate; the plurality of second pads are bonded with a circuit board; the second pads and the conductive layer are arranged on a same film layer; and the oxidization protective layer is arranged on a side, facing away from the base substrate, of the plurality of second pads;
wherein the array substrate further comprises a first routing wire layer arranged between the plurality of first pads and the base substrate;
the first routing wire layer comprises a first metal layer, a first routing wire sub-layer and a second metal layer which are arranged in a stacked mode;
the plurality of first pads are electrically connected with the second metal layer, and the plurality of second pads are electrically connected with the second metal layer; and
materials of the first metal layer and the second metal layer comprise a molybdenum-niobium alloy, and a material of the first routing wire sub-layer comprises copper.

2. The array substrate according to claim 1 , wherein the material of the oxidization protective layer further comprises nickel.

3. The array substrate according to claim 2 , wherein the material of the oxidization protective layer further comprises copper.

4. The array substrate according to claim 2 , wherein the material of the oxidization protective layer further comprises at least one type of other metal materials of which a lattice constant has a difference between 0.1 and 0.6 from a lattice constant of the copper.

5. The array substrate according to claim 4 , wherein a crystal form of each of the other metal materials is face-centered cubic or body-centered cubic; and
a thermal diffusivity of each of the other metal materials is greater than a thermal diffusivity of the copper.

6. The array substrate according to claim 5 , wherein the other metal materials comprise titanium, molybdenum or aluminum.

7. The array substrate according to claim 4 , wherein a thickness of the oxidization protective layer ranges from 30 nm to 150 nm.

8. The array substrate according to claim 1 , wherein the functional region further comprises:
a first passivation layer arranged between the first routing wire layer and the plurality of first pads;
a first flat layer arranged between the first passivation layer and the plurality of first pads;
a second flat layer arranged on a side surface of the oxidization protective layer; and
a first connection portion arranged on the oxidization protective layer;
wherein the second flat layer covers a region among the plurality of first pads.

9. The array substrate according to claim 8 , wherein the bonding region further comprises:
a second passivation layer arranged between the first routing wire layer and the plurality of second pads;
a third flat layer arranged between the second passivation layer and the plurality of second pads;
a fourth flat layer arranged on a side surface of the oxidization protective layer; and
a second connection portion arranged on the oxidization protective layer;
wherein the fourth flat layer covers a region among the plurality of second pads; and
the third flat layer and the first flat layer are arranged on a same layer, the fourth flat layer and the second flat layer are arranged on a same layer, and the second passivation layer and the first passivation layer are arranged on a same layer.

10. The array substrate according to claim 8 , wherein the plurality of first pads are divided into a plurality of first pad groups, and each of the plurality of first pad groups comprises a cathode pad and an anode pad which are arranged pairwise; and
the second region in the conductive layer is configured to realize series connection or parallel connection of the plurality of first pad groups and further configured to be electrically connected with the first routing wire layer through a via hole penetrating through the first flat layer and the first passivation layer.

11. The array substrate according to claim 1 , further comprising a protective layer arranged on a side, facing away from the base substrate, of the plurality of first pads and the plurality of second pads;
wherein the protective layer is exposed out of the plurality of first pads and the plurality of second pads; and
a material of the protective layer comprises silicon nitride or silicon oxide.

12. The array substrate according to claim 1 , wherein
the functional region comprises a thin-film transistor arranged on the base substrate;
the thin-film transistor comprises a source-drain electrode layer; and
the source-drain electrode layer and the conductive layer are arranged on a same layer and made of a same material.

13. A display apparatus, comprising: the array substrate according to claim 1 .

Assignees

• Boe Technology Group Co Ltd

Inventors

• He Jiayu
• Ning ce
• Li Zhengliang
• Hu hehe
• Huang Jie
• Yao Nianqi
• Zhao Kun
• Li Feifei
• Lei Liping
• Qi Qi

Classifications

• H10D86/441 Primary

  Interconnections, e.g. scanning lines · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title