Transistors, array of transistors, and array of memory cells individually comprising a transistor

Patent metadata

Field	Value
Publication number	US-12439637-B2
Application number	US-202217695634-A
Country	US
Kind code	B2
Filing date	Mar 15, 2022
Priority date	Dec 27, 2021
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

A transistor comprises a pair of source/drain regions having a channel region there-between. A gate is adjacent the channel region with a gate insulator being between the gate and the channel region. A fixed-charge material is adjacent the source/drain regions. Insulating material is between the fixed-charge material and the source/drain regions. The insulating material and the fixed-charge material comprise different compositions relative one another. The fixed-charge material has charge density of at least 1×1011 charges/cm2.

First claim

The invention claimed is:

1. A transistor comprising:
a pair of source/drain regions having a channel region there-between;
a gate adjacent the channel region with a gate insulator being between the gate and the channel region, the gate having an external surface that is not between the gate and the channel region;
a fixed-charge material that is along the external surface of the gate and that is adjacent the source/drain regions; and
insulating material between the fixed-charge material and the source/drain regions, the insulating material and the fixed-charge material comprising different compositions relative one another, the fixed-charge material having charge density of at least 1×10 11 charges/cm 2 .

2. The transistor of claim 1 wherein the fixed-charge material has charge density no greater than 1×10 14 charges/cm 2 .

3. The transistor of claim 1 wherein the fixed-charge material has charge density of 2×10 12 to 5×10 12 charges/cm 2 .

4. The transistor of claim 1 wherein the source/drain regions individually comprise conductivity-increasing dopant therein of 5×10 17 to 5×10 19 atoms/cm 3 and adjacent which the fixed-charge material is.

5. A transistor comprising:
a pair of source/drain regions having a channel region there-between;
a gate adjacent the channel region with a gate insulator being between the gate and the channel region;
a fixed-charge material adjacent the source/drain regions;
insulating material between the fixed-charge material and the source/drain regions, the insulating material and the fixed-charge material comprising different compositions relative one another, the fixed-charge material having charge density of at least 1×10 11 charges/cm 2 ; and
the source/drain regions individually comprising a highest-conductivity region and an L DD region between the highest-conductivity region and the channel region, the insulating material and the fixed-charge material being over the L DD regions.

6. The transistor of claim 5 wherein the insulating material in a vertical cross-section is over all of longest linear-lengths of the L DD regions.

7. The transistor of claim 6 wherein the fixed-charge material in the vertical cross-section is over all of the longest linear-lengths of the L DD regions.

8. The transistor of claim 5 wherein the insulating material in a vertical cross-section is over more of longest linear-lengths of the L DD regions than over longest linear-lengths, if any, of the highest-conductivity regions.

9. The transistor of claim 8 wherein the fixed-charge material in the vertical cross-section is over more of the longest linear-lengths of the L DD regions than over the longest linear-lengths, if any, of the highest-conductivity regions.

10. The transistor of claim 9 wherein the fixed-charge material in the vertical cross-section is not over any of at least one of the highest-conductivity regions.

11. The transistor of claim 1 wherein the fixed-charge material is directly against the insulating material.

12. The transistor of claim 1 wherein the fixed-charge material is not directly against the insulating material.

13. A transistor comprising:
a pair of source/drain regions having a channel region there-between;
a gate adjacent the channel region with a gate insulator being between the gate and the channel region;
a fixed-charge material adjacent the source/drain regions;
insulating material between the fixed-charge material and the source/drain regions, the insulating material and the fixed-charge material comprising different compositions relative one another, the fixed-charge material having charge density of at least 1×10 11 charges/cm 2 ; and
the fixed-charge material being directly against the gate.

14. The transistor of claim 1 wherein the fixed-charge material is not directly against the gate.

15. The transistor of claim 1 wherein the fixed-charge material is not directly against the source/drain regions.

16. A transistor comprising:
a pair of source/drain regions having a channel region there-between;
a gate adjacent the channel region with a gate insulator being between the gate and the channel region;
a fixed-charge material adjacent the source/drain regions;
insulating material between the fixed-charge material and the source/drain regions, the insulating material and the fixed-charge material comprising different compositions relative one another, the fixed-charge material having charge density of at least 1×10 11 charges/cm 2 ; and
the gate insulator and the insulating material being of the same composition relative one another.

17. The transistor of claim 1 wherein the gate insulator and the insulating material are not of the same composition relative one another.

18. The transistor of claim 1 wherein the gate insulator and the insulating material are of the same thickness relative one another.

19. The transistor of claim 1 wherein the gate insulator and the insulating material are not of the same thickness relative one another.

20. A transistor comprising:
a pair of source/drain regions having a channel region there-between;
a gate adjacent the channel region with a gate insulator being between the gate and the channel region;
a fixed-charge material adjacent the source/drain regions;
insulating material between the fixed-charge material and the source/drain regions, the insulating material and the fixed-charge material comprising different compositions relative one another, the fixed-charge material having charge density of at least 1×10 11 charges/cm 2 ; and
the transistor being vertical.

21. The transistor of claim 1 wherein the transistor is horizontal.

22. A transistor comprising:
a pair of source/drain regions having a channel region there-between;
a gate adjacent the channel region with a gate insulator being between the gate and the channel region;
a fixed-charge material adjacent the source/drain regions;
insulating material between the fixed-charge material and the source/drain regions, the insulating material and the fixed-charge material comprising different compositions relative one another, the fixed-charge material having charge density of at least 1×10 11 charges/cm 2 ; and
the transistor being volatile.

23. An array of transistors, the transistors individually comprising the transistor of claim 1 .

24. An array of memory cells, the memory cells individually comprising the transistor of claim 1 .

25. A transistor comprising:
a pair of n-type source/drain regions having a channel region there-between;
a gate adjacent the channel region with a gate insulator being between the gate and the channel region, the gate having an external surface that is not between the gate and the channel region;
a positive fixed-charge material that is along the external surface of the gate and that is adjacent the n-type source/drain regions; and
insulating material between the positive fixed-charge material and the n-type source/drain regions, the insulating material and the positive fixed-charge material comprising different compositions relative one another, the positive fixed-charge material comprising at least one of silicon nitride and a lanthanide-series oxide.

26. A transistor comprising:
a pair of p-type source/drain regions having a channel region there-between;
a gate adjacent the channel region with a gate insulator being between the gate and the channel region;
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Assignees

• Micron Technology Inc

Inventors

• Karda Kamal M
• Liu Haitao
• Chhajed Sameer

Classifications

• H10D30/6728

  Vertical TFTs · CPC title

• H10B12/31

  having a storage electrode stacked over the transistor · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title