Semiconductor device and manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-12439622-B2
Application number	US-202218069203-A
Country	US
Kind code	B2
Filing date	Dec 20, 2022
Priority date	Feb 2, 2022
Publication date	Oct 7, 2025
Grant date	Oct 7, 2025

Abstract

Provided is a semiconductor device including a gate trench portion and a first trench portion adjacent to the gate trench portion. The device may include a first conductivity type drift region provided in a semiconductor substrate, a second conductivity type base region provided above the drift region, a first conductivity type emitter region provided above the base region and having a doping concentration higher than that of the drift region, and a second conductivity type contact region provided above the base region and having a doping concentration higher than that of the base region. The contact region includes a first contact portion provided on a front surface of the substrate, and a second contact portion having a doping concentration different from that of the first contact portion and provided alternately with the first contact portion in a trench extending direction on a side wall of the first trench portion.

First claim

What is claimed is:

1. A semiconductor device comprising a gate trench portion and a first trench portion adjacent to the gate trench portion, the semiconductor device comprising:
a drift region of a first conductivity type, which is provided in a semiconductor substrate;
a base region of a second conductivity type, which is provided above the drift region;
an emitter region of the first conductivity type, which is provided above the base region and has a doping concentration higher than a doping concentration of the drift region; and
a contact region of the second conductivity type, which is provided above the base region and has a doping concentration higher than a doping concentration of the base region,
wherein the contact region includes a first contact portion provided on a front surface of the semiconductor substrate, and a second contact portion which has a doping concentration different from a doping concentration of the first contact portion and is provided alternately with the first contact portion in a trench extending direction on a side wall of the first trench portion.

2. The semiconductor device according to claim 1 , wherein
the first contact portion is provided to extend from the gate trench portion to the first trench portion on the front surface of the semiconductor substrate.

3. The semiconductor device according to claim 1 , wherein
the second contact portion is provided below the emitter region.

4. The semiconductor device according to claim 1 , wherein
the second contact portion is provided to extend from the first trench portion to below a lower end of the emitter region in a trench array direction.

5. The semiconductor device according to claim 4 , wherein
the second contact portion is in contact with the lower end of the emitter region.

6. The semiconductor device according to claim 3 , wherein
the second contact portion is set apart from the gate trench portion, below the emitter region.

7. The semiconductor device according to claim 3 , wherein
the second contact portion is set apart from the gate trench portion by 0.6 μm or more in a trench array direction, below the emitter region.

8. The semiconductor device according to claim 1 , wherein
the first contact portion and the second contact portion are provided on the front surface of the semiconductor substrate at the side wall of the first trench portion.

9. The semiconductor device according to claim 1 , wherein
the doping concentration of the first contact portion is higher than the doping concentration of the second contact portion.

10. The semiconductor device according to claim 1 , wherein
the doping concentration of the first contact portion is lower than the doping concentration of the second contact portion.

11. The semiconductor device according to claim 1 , wherein
the doping concentration of the second contact portion is lower than the doping concentration of the emitter region.

12. The semiconductor device according to claim 1 , wherein
a lower end of the second contact portion is shallower than a lower end of the first contact portion in a depth direction of the semiconductor substrate.

13. The semiconductor device according to claim 1 , wherein
a lower end of the second contact portion is deeper than a lower end of the first contact portion in a depth direction of the semiconductor substrate.

14. The semiconductor device according to claim 1 , wherein
the first contact portion includes a low concentration region having a doping concentration, and a high concentration region which has a doping concentration higher than the doping concentration of the low concentration region and is provided between the low concentration region and the second contact portion on the front surface of the semiconductor substrate, and
the doping concentration of the high concentration region is higher than the doping concentration of the second contact portion.

15. The semiconductor device according to claim 1 , comprising
an interlayer dielectric film provided above the semiconductor substrate,
wherein the emitter region is connected to an emitter electrode via a contact hole provided penetrating through the interlayer dielectric film.

16. The semiconductor device according to claim 15 , wherein
the second contact portion extends beyond the contact hole from the first trench portion in a trench array direction.

17. The semiconductor device according to claim 1 , wherein
the first trench portion is a dummy trench portion set at an emitter potential.

18. The semiconductor device according to claim 1 , wherein
the first trench portion includes a dummy gate trench portion which is set at a gate potential and is not in contact with the emitter region.

19. The semiconductor device according to claim 1 , wherein
the first trench portion is a gate trench portion which is set at a gate potential and is in contact with the emitter region.

20. The semiconductor device according to claim 19 , wherein
the emitter region includes a first emitter region which is in contact with the gate trench portion and is set apart from the first trench portion in a mesa portion between the gate trench portion and the first trench portion, and
the contact region is provided below a lower end of the first emitter region on a side of the first trench portion in the mesa portion.

21. The semiconductor device according to claim 20 , wherein
the emitter region includes a second emitter region which is in contact with the first trench portion and is set apart from the gate trench portion in the mesa portion, and
the contact region is also provided below a lower end of the second emitter region on a side of the gate trench portion in the mesa portion.

22. The semiconductor device according to claim 21 , wherein
the first emitter region and the second emitter region are alternately provided in the trench extending direction of the gate trench portion.

23. The semiconductor device according to claim 1 , wherein
in a cross section parallel to the front surface of the semiconductor substrate,
at least a part of a boundary between the second contact portion and the base region is spaced apart from a side wall of the gate trench portion, and
the boundary has a portion in which a distance between the boundary and the side wall of the gate trench portion decreases as approaching toward the first contact portion from a portion at which the distance is at a maximum.

Assignees

• Fuji Electric Co Ltd

Inventors

• Mitsuzuka Kaname
• SHIRAKAWA Tohru

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10P30/204 Primary

  into Group IV semiconductors · CPC title

• H10D64/231

  Emitter or collector electrodes for bipolar transistors · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/133

  Emitter regions of BJTs · CPC title